Analysis and Key Figures of Merit

Data is extracted from C-V and conductance data. Once the data has been imported and conditioned, key data required for further analysis is extracted: oxide capaci- tance (Cox), flatband voltage (VF B) and bulk Fermi level. As the dielectric thickness

and relative permittivity (dielectric constant) cannot be determined with sufficient accuracy to calculateCox, it is extracted using the method detailed in section 5.3.2.

VF B is then extracted by determining CF B via C-V modelling (as described in sec-

tions 4.4.2 and 5.2) and searching the measured response (at high frequency) for a match to this capacitance value (with linear interpolation used to extract a more accurate value). This model also generates a value for bulk Fermi level. The critical figure of merit is interface-trapped charge density (Dit) and it is extracted using the

For the Terman method, a modelled C-V response is generated, as described in sections 4.4.2 and 5.2, using the extractedCox value, as well as the set temperature

and the dopant concentration (taken from the wafer conformance certificate or from Hall measurement for epitaxial material, described in section 5.3.1). This modelled response (at high frequency) is then compared to the measured response point-by- point as described in section 4.3.2, with linear interpolation used to ensure a more accurate stretch-out value. The extracted Dit values are mapped to energy levels,

using the ψs values associated with each modelled capacitance point, to give a full

Dit profile.

The high-low method also requiredCox to be known but it additionally requires

VF B to enable the integral from equation 4.12 to be used. By applying equations

4.4 and 4.12 to each measured data point, a Dit profile is extracted. The high-low

method frequently underestimatesDitwhen compared to other methods and is more

prone to large disruptions, and so data from the high-low method is not included in the studies presented in this thesis.

For the conductance method, the density of states in the valence and conduction bands are first calculated from materials data and temperature, as well as the ther- mal velocity of electrons and holes. Trap capture cross-section data is unavailable for InSb - Engel-Herbertet al.[23] note that the sensitivity of energy mapping to this parameter is low,∼60 meV per decade at room temperature and lower at cryogenic temperature, and the value they report for InGaAs is taken as an approximation. The magnitude of extracted Dit is unaffected. Following calculation of material

data, the conductance data is normalised, as subsequent calculations use GP

ω rather

than G. A 3D plot of G

ω against voltage and frequency is shown in figure 5.3 for

a typical device measured with high resolution in voltage and frequency at 80 K. The characteristic Dit ‘ridge’ feature can be seen in light blue but an additional

hillock feature, visible in green/yellow/red, normally appears at extreme negative gate voltage, attributed to slow states and/or leakage. For the purposes of Dit ex-

traction, the hillock feature is omitted and the ‘ridge’ feature isolated by using a 3-dimensional reference feature, generated using exponential functions. MATLAB’s ‘goodness of fit’ function is then used to scan for the region in the G_ω data that best matches this reference signal and this region is taken for subsequent analysis. Twin iteration loops then scan each frequency for the maximum GP

ω value. This peak

value is converted to aDit value using equation 4.25 and the energy level associated

with it determined using equation 4.28 and the frequency it occurs at. This process is then repeated for all frequencies, generating aDit profile.

-6 -4 -2 0 2 4 6 1 02 1 03 1 04 1 05 1 06 -1x 10 -8 0 1 x10 -8 2x10 -8 3x10 -8 4x10 -8 5x10 -8 6x10 -8 7x1 0 -8 F re q u e n c y (H z ) G / w ( S c m - 2 r a d - 1 s ) V o lta g e (V )

Figure 5.3: 3D surface plot of normalised conductance-voltage-frequency data

is extracted for a forwards-direction sweep of DC voltage (normally from inversion to accumulation, eliminating ’deep depletion’ features from residual minority carri- ers) but an additional reverse-direction sweep is often taken. The flatband voltage extracted from the reverse sweep is often different to the forward sweep, i.e. the response displays hysteresis. Hysteresis voltage (VH) is extracted at CF B and all

the Dit and VF B extraction techniques performed on the forward sweep are also at-

tempted on the reverse sweep data. This potentially gives 6Ditprofiles, although the

standard measurement procedure does not collect enough conductance data when performing the reverse sweep to perform a meaningful conductance Dit extraction

(as the measurement would become excessively long). Hysteresis effects are assumed to be due to trap states with a long time constant, longer than 1 s, which do not relax to equilibrium until the DC voltage sweep (in one direction) has completed.

Three other ‘alternative’ figures of merit are included in data extraction and occa- sionally studied for analysis: capacitance modulation at low frequency, capacitance modulation at high frequency and frequency dispersion in accumulation. These fig- ures of merit are less reliable and/or less well-characterised than Dit, VF B and VH

but occasionally offer alternative perspectives or show trends to support other fig- ures of merit. Capacitance modulation at low frequency - i.e. the ratio between maximum and minimum capacitance in the low frequency regime - can be taken as a simplified approximate indicator of Dit, following the same principles as the

high-low method, described in section 4.3.1. Capacitance modulation at low fre- quency is occasionally quoted as a figure of merit as a simplified alternative to the

high-low method, and its extraction allows comparison with such data, but for this thesis it is superseded by theDit extracted by the Terman and conductance meth-

ods. Capacitance modulation at high frequency can be used as a check for unwanted generation-recombination in the inversion regime, as this would raise the minimum capacitance. Finally, slow ‘near interface’ trap states are known to cause frequency dispersion in accumulation[54] and this dispersion can be quantified as an average percent per decade as a method of quantifying the influence of slow traps. While these figures of merit are included in data extraction they present several issues: they are normally superseded by other methods or not relevant; they show high sensitivity to noise and extraction uncertainty and low sensitivity to treatments and processes; and, as such, they show correlations with process treatments weakly and/or infrequently. They are mentioned here for completeness but only frequency dispersion is mentioned in this thesis, in chapter 9.