Appendix Section

Appendix A RASI Chart

Responsibility

Legend Requirement SUPPLIER

GE Supplier Quality GE Sourcing/ Procurement GE Engineering Prior to Business Award:

· GE Business Survey. Minimum score

required: 90%. S,I R,A S

· Conduct GE Process Survey. Min Score

required 80%. S,I R,A S

2. Complete for Prototype build approval:

· Initial Process Review R,I A S

· Design Guidance/DFM and DFT Data R,I S A

· Preliminary Bill of Material S,I A R

· Process Material Specifications and MSDS R,I A S

· Process Flow Description R,I A S

· Bare PCB Qualification R,I A S

· Preliminary Board and Process Cleanliness R,I A S

· ICT and FCT Preliminary Description R,I A S

Complete for Pre Pilot build approval:

· GE Material Scheduling and delivery R,I S,A

· Failure Analysis and Corrective Action

System R A

· Special Process and Testers Qualifications _{R A S,I}

· First Piece Reports R,I A S,A

· Autopsy Scorecard and Process Yield

Data/DPMO R,I S,A

· Reliability Qualification Testing R A S,I

· Reliability Production Audit R A S,I

· Process FMEA R,I A

· Quality Control Plan R,I A

· Gage R&R and Capability Studies R,I A

· Supplier Process Quality (SPQ) Data Plan R,I A S

· Ionic Chromatography Testing R,I A S

· Shipping Package Design R,I A S

· Production Readiness Review S,I R I

Complete for Pilot/Production Build Approval

· GE Production material POs received I S R,A

· SPQ - CTQS Definition R,I A S

· Close all open FPR items / Pilot run

Samples shipment R,I A S

· Agency Approvals (i.e. UL, etc) _{R,I A S}

· Close all remaining items. R,I A S

Post-Production Activities

· Production Reliability Audit R A S,I

· ESS and HASS R A S,I

· Supplier Process Data Flow (SPC) R A

· Process Yield Data/DPMO R A

· Process Cleanliness Audit R A S

· Full Traceability R A

· Incoming Inspection and Spot Buy

Process R A

· Bow and Twist Inspection R A

· Change control Process R S I A

· Solder Paste Printing Inspection R A

· BGA Underfill R A I

· Solder joint Inspection R A

· Rework process R A

· Quality Targets (PPMs) R,I A S

· Quality Management System and

Internal Audits _{R,I A}

· GE Annual Quality Audits R,I A

· ROHS/REACH certification R,I A S

Agility Specification

Supplier Responsiveness to Quality Events R,I A S

R= Responsible A= Approver S= Support I= Information

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Appendix B: PCB/PCBA Cleanliness Specification

1.1. Purpose

This section outlines GE Digital Meters Printed Circuit Board Assembly (PCBA) Cleanliness testing

requirements, PCB/PCBA sample testing to be conducted, the data collection procedure, the method of analysis, definition of specification limits of each ion of concern and direction on action to take when levels are exceeded. In the event of conflict between the requirements of this document and the referenced applicable documents listed below, this document governs and takes precedence.

1.2. Scope

This section covers the following:

 Starting a new assembly line

 Qualifying or switching to a new Printed Circuit Board (PCB) supplier

 Changing a PCB Supplier process or materials

 Qualifying a new Contract Manufacturer (CM) / Commodity (FPQ) (Pilot Run)

 Qualifying a new PCB and/or PCBA Design

 Verifying the quality of manufactured PCBAs to ensure the CM has maintained the quality of work

1.3. Definition & Acronyms

 CM – Contract Manufacturer

 Ion Chromatograph - Measures the amount of ionic contamination that is present on the

surface of the PCB. Ionic contamination is a concern due to the relationship between high contamination levels and failure of the PCB due to electro migration.

 PCB – Printed Circuit Board

 PCBA – Printed Circuit Board Assembly

 SMT – Surface Mount Technology

 SQE – Supplier Quality Engineer

 Via – conductor which electronically connects one or more layers of a PCB or PCBA

 WOA – Weak Organic Acid

1.4. Responsibility

 Contract Manufacturer ensures this specification is followed

 Supplier Quality – Ensures CM compliance with this specification; receives and store cleanliness reports from third-party testing laboratory.

 Third-Party Testing Laboratory performs cleanliness per IPC-TM-650 2.3.28A on samples submitted by CM.

 Engineering analyzes data from the Third-Party Testing Lab. and takes action when results indicate a failure

 Sourcing distributes this specification to Contract Manufactures

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1.5. Procedure

1.5.1. Samples & Data collection: Depending on the origin of the requirement, CM must collect and submit the following quantity of samples:

1.5.1.1 On Going production - Quarterly audits:

The PCBA Contract Manufacturer’s location site submits to the GE designated Testing Lab or use certified C3 Tester, the following sample for cleanliness testing on a quarterly basis:

 1 Raw PCB panel directly from PCB supplier.

 1 Processed PCB per part family from incoming inspection at CM , run through Reflow and Wave soldering processes and after wash process if applicable without conformal coating and

components.

 In cases where there are multiple part families, alternate samples from varying part families each quarter, so that all part families are tested at a minimum annually. Part Families must be defined by GE PCB part number or PCB vendor, pcb finish, and PCB material.

1.5.1.2 PCB Engineering Changes

The PCBA Contract Manufacturer’s location site submits to the GE designated Testing Lab or use certified C3 Tester, the following sample for cleanliness testing for qualified CMs supplying PCBAs to GE, for qualification of a modification to the PCB and/or PCBAs processes affecting form, fit or function:

 1 Raw PCB directly from PCB Supplier, if qualification is due to PCB change.

 1 Processed PCB per part family from PCBA CM, run through Reflow and Wave soldering processes and after wash process if applicable without conformal coating and components.

1.5.1.3 New PCB Supplier or new PCB Manufacturing location or NPI Qualification:

The PCBA Contract Manufacturer’s location site submits to the GE designated Testing Lab the following sample for cleanliness testing for new CM qualification or qualification of new PCB suppliers or PCB / PCBA design the sample size is:

 5 unprocessed PCB ( Raw PCBs ) directly from PCB supplier.

 5 Processed PCB from PCBA CM, run through Reflow and Wave soldering processes and after wash process if applicable without conformal coating and components.

1.5.1.4 Sample handling

Once removed from the CM normal manufacturing process, the samples must be handled with clean cotton gloves or clean-room vinyl gloves in order to keep contaminants (hands, oils, salts, etc.) from being transferred to the PCB and PCBA samples.

Place sample PCBs/PCBAs either in a KAPAX bag or wrap in new aluminum foil prior to placing in a sealed bag and packaging for shipment to the Testing Lab. Send packaged samples to the following test lab.

Foresite

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1.5.2. Cleanliness Testing

The testing lab assesses the PCB/PCBA samples provided by GE contract manufacturers as follows:

1.5.2.1. Areas of Investigation

Bare PCB: sample three areas plus the whole board

1. Board surface

Processed PCBAs: sample six areas plus the whole board

1. Board Surface

2. During Failures Analysis investigation, C3 extraction under components and between

layers.

1.5.2.2. Test Procedure

Ionic Chromatography test procedure as defined per IPC-TM-650 2.3.28A. Static Rose (Omegameter) test procedure as defined per IPC-TM-650 2.3.25.1. Localize extraction will be performed using the C3 tester equipment.

C3 audit testing can be performed at 2 different levels; normal standard reliability (60 seconds at 500 uA of leakage current ) or High Reliability (120 seconds at 250uA of leakage current ) . Levels for passing audit testing will be determined initially by GE and control documentation will reflect this Pass/Fail criteria.

1.5.2.3 Definitions

1. Bare Board : Is designated as a PCB ( Printed Circuit Board ) that has been

fabricated only . Fabrication is etching, drilling, plating, soldermask and adding a surface finish protectant.

2. Processed – No Clean Board : Is a PCB that doesn’t use an aqueous wash process

for removing flux residues at the PCBA manufacturer.

 For C3 testing – PCB shall have reflow/wave processes (flux and soldering) if

these are the normal process for that PCB. Components should be added unless otherwise specified by GE.

 For IPC –TM-650 2.3.28 – PCB bag method. PCB shall have reflow/wave

processes (flux and soldering) if these are the normal process for that PCB. Components should not be added.

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3. Processed – Clean Board : Is a PCB that uses an aqueous process to remove flux

residues at the PCBA manufacturing.

 For C3 testing – PCB shall have reflow/wave processes (flux and soldering) if

these are the normal process for that PCB. Components should be added unless otherwise specified by GE.

 For IPC –TM-650 2.3.28 – PCB bag method. PCB shall have reflow/wave

processes (flux and soldering) if these are the normal process for that PCB. Components should not be added.

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1.5.2.4 Specification Limits Ionic Chromatography levels must not exceed the following levels:

Static Rose (Omegameter) levels must not exceed the following levels:

Contaminants Board Bare

(μg/in2₎ Processe d No Clean Board (μg/in2₎ Processed Clean Board (μg/in2₎ Sodium Na+ _{<3 <3 <3} Potassium K+ _{<3 <3 <3} Calcium Ca+2 _{<1 <1 <1} Magnesium Mg+2 _{<0.5 <1 <1} Ammonium NH4+ <2 <2.5 <2.5 Acetate CH_O- 3CO <2.5 <3 <3 Formate HCOO- <2.5 <3 <3 Bromide Br- _{<3 <6 <6} Chloride Cl- _{<2.5 <3.5 <3.5} Fluoride F- _{<0.5 <1 <1} Nitrate NO3- <2 <3 <3 Nitrite NO2- <2 <3 <3 Lithium Li <0.5 <1 <1 Sulfates SO4-2 <3 <3 <3 Citrate <0.5 <2 <2 Phosphate PO4-3 <2 <3 <3 WOA WOA - SMT N/A 25 25 WOA- WAVE N/A 150 25 Contaminants Bare Board (μg/in2₎ Processed Board (μg/in2₎

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1.6. Outputs

1.6.1. Test Report

GE designated Testing Lab documents the test results and sends a report to the CM which initiated the testing or C3 Test Results the CM submits the test report to the GE SQE.

1.6.2. Test Results Analysis:

Analysis of the report is conducted by the SQE. In case the maximum values listed in the above table are exceeded:

 If qualifying a new PCB Manufacturer or a new PCBA Contact Manufacturer or a

process/material change at current CM, then the qualification is rejected until corrective action is implemented and proven effective through subsequent testing.

 If during audit testing of current product, then the lots of printed circuit boards associated with the failed board must be placed into non-conforming material. Supplier Quality Engineer will follow GEE-501 Supplier Deviation and Request for Information Process.

 The test report and all reviewed outcomes are filed and stored as quality records by Supplier Quality using the naming convention: (P/N)_(PCBA CM)_(PCB CM)_IC Report

Number_mmddyyyy. Records are stored in folder

http://libraries.ge.com/foldersIndex.do?entity_id=7053282101&sid=101#21973385101 Records are maintained for a minimum of three years after the year of creation (records created in 2012 may not be deleted until January 1, 2016).

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Appendix C: Production Reliability Audit Testing (PRAT) Specification

1.0 Purpose

Establishes procedures to ensure consistent, ongoing reliability of printed circuit board assemblies after initial qualification, and prevent significant failure rates due to insufficient product reliability. A “significant” failure rate is any greater than 10% in 10 years of life. It outlines the minimum requirements for ongoing product reliability audit testing of printed circuit board assemblies produced for GE Energy Management applications; how audit test specifications and failure criteria are defined; and how appropriate reporting and alarming will be conducted in response to such failures.

2.0 Scope

The procedures are developed to target three types of excursions, and to detect them within 2 to 3 months of printed circuit board production:

• Catastrophic failures due to inferior components (such as unauthorized sub-tier supplier changes) • Wide excursions in some previously controllable variable (process drift at the CM)

• Shift in the overall quality (systemic drift at the CM or sub tier supplier)

3.0 Definitions and Acronyms 3.1 Acronyms

 ALT - Accelerated Life Test (85/85 Chamber Test)

 BOM - Bill of Materials

 CM - Contract Manufacturer

 EAU - Estimated Annual Usage

 PCBA - Printed Circuit Board Assembly

 PRAT - Product Reliability Audit Testing

 QCP - Quality Control Plan

 SPQ - Supplier Production Quality system

 SQE - Supplier Quality Engineer

1.2 Definitions

 Audit Period - Timeframe over which the representative sample lot is collected and during which the audit population is produced. There should be no discontinuity of audit periods; the start date of one audit period should immediately follow the end date of the prior audit period.

 Audit Population - Product represented by a particular set of test results from a particular sample lot on a particular ALT cycle.

 Failure Review Team - SQE, SQE Team Leader, Design Engineer, Office of the Chief Engineer, Reliability Engineer

 Sample Lot - A rationally sub-grouped collection of samples in accordance with Section 6.5.3 of one part number, representing one audit population, which will be tested together in one ALT cycle, representing one audit period.

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 Suspension Check - The required, weekly suspension of each PRAT chamber test to check 100% of the sample lot on test for failures, as stipulated by the ALT specification for that board.

4.0 Responsibility

• Supplier Quality is the primary contact who determines when a part is required to have PRAT. • Engineering is the primary contact for development of ALT specification Documentation.

• Contract Manufacturer is the primary contact for developing GE approved access to environmental test capability to meet specification.

5.0 Inputs

• ALT Specification Document

• Environmental Test Chamber Capability. • Production parts.

6.0 Procedure

6.1 Quality Requirements for PRAT Specification – The SQE ensures an effective PRAT Specification is provided to the CM’s, which enables them to effectively implement, and exercise PRAT. The key deliverables are selection of PCBAs for PRAT, PRAT test outline, and collection of technical information.

6.1.1 Selection of PCBAs for The PRAT Program – The SQE selects part numbers for the PRAT Program. It is not practical to require testing for each and every PCBA part number. The ideal selection of part numbers utilizes a minimum number of part numbers on test while covering a maximum number of high-EAU part families, CM’s, components, and sub-tier suppliers (in that order of priority).

6.1.1.1 The SQE should first select any PCBA family with EAU greater than 100K. Second, each CM producing this family should be represented - select each CM’s most populated version within that family. This provides a wide and efficient coverage of each family, for each CM and their respective supply chains.

6.1.1.2 There are other circumstances the SQE should take into consideration beyond, EAU, CM coverage, when choosing part numbers for the PRAT Program:

• Part numbers at risk of becoming problematic (new technology, new design, etc.)

• High historical failures

• Designs of higher complexity • First time CM’s or Sub-tier suppliers • New components

6.1.1.3 Special Circumstances in PCBA Selection - There are special circumstances, which may prevent the straightforward selection procedure outlined above, or present opportunities for more efficient part number selection, Some examples are listed below:

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• Masked IC – this prevents ALT software from being programmed, and can make PRAT impossible for such part numbers. Ideally, another means of PRAT could be identified for that part’s components and sub-tiers at all CM’s.

• Insufficient acceleration factor - some failure modes are impossible to accelerate in ALT, inherent to the design and application. It is important that this is made clear by the Design Engineer – See Section 6.2. Ideally, another means of PRAT could be identified for any such failure mode determined to be of significant concern, at all CM’s.

• Production mix – in some instances, a CM may have a discontinuous production schedule with infrequent, large runs of the only part number with a Flash IC (a service board). This can make sub-grouping across one part number and/or one period difficult. In this case, revisit alternative production schedules and customize rational sub-grouping procedures. It may sometimes be prudent to identify different part numbers within a PCBA family when part number EAUs are small.

• Common-BOM/Design optimization – If two board families are being

considered for PRAT, and it can be shown that the BOMs and/or designs for these parts are sufficiently similar, then one part may be shown to be representative for both, eliminating the need to PRAT the other. It should be kept in mind that such optimization may be possible at one CM but not another, for a particular part number, due to the product mix for each CM. 6.1.2 PRAT Test Outline - The SQE stipulates the number of boards, and test duration required to

demonstrate 90% Reliability, 90% Confidence, for 10 Years of Life. This 90% confidence of 90% reliability should be accomplished by requiring a 10-year test (based on application and platform-specific acceleration factors) with one of the following criteria sets:

• Test 22 or more samples with 0 failures,

6.1.3 Collection and Review of Technical Information - The SQE facilitates discussion with the Design Engineer, who will provide the technical details outlined in Section 6.2, in an ALT specification specific to each part number. The SQE reviews and approves the ALT specification at the Spec Peer Review, paying particular attention to:

• Failure modes not accelerated

• Any suggestions made by the Design Engineer for BOM/Design Optimization • Clarity, and thoroughness for use by the CM

• Understanding any unique failure modes (and root cause procedures) inherent to a particular part number design

Once the SQE has the completed document, the SQE will ensure that the CM meets all specifications.

6.2 Technical Requirements for PRAT Specification

6.2.1 The Design Engineer supports the SQE by generating the ALT specification, which should provide all technical information, necessary for PRAT. Each ALT specification must pass ALT Spec Peer-Review. At a minimum, the ALT specification must include the following:

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 Identify any differences in load condition between the PRAT ALT and the expected worst case application

 List of any suggestions for other possible part numbers which may be represented by this part number (BOM/Design Optimizations)

 Provide definitions, and all documents necessary to design and construct all required load systems, and fixtures

 Provide software and all necessary instructions on preparation of PCBA samples

 Detailed special-case root cause procedures that should be initiated in the event of a failure

6.3 PRAT Procedures at The Contract Manufacturer

6.3.1 The CM to ensure all aspects of this document, and ALT specification are strictly followed, and that the intent of the PRAT Program is satisfied to the best of the CM’s ability. The intent is that the CM ensure every reasonable effort is made to maintain continuous, uninterrupted testing and sample collection, so that for every part number identified for PRAT, all production periods are represented by a specific sample lot. Other than suspension checks and

reasonable times replacing one sample lot with another, there should be no interruption in testing for any part number requiring PRAT. Other than unavoidable circumstances, samples should be rationally sub-grouped in accordance with Section 6.3.2. If there are extenuating circumstances, making this impractical, written approval from the SQE is required. In all PRAT matters, the SQE is the primary point of contact for the CM.

6.3.2 Rational Sub-Grouping of Samples - The practice of rational sub-grouping by the CM is

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