Architecture

Figure 3-1 provides a high level description of the MPLS processor. Data is written to the processor through the write and writedata signals. The read and readdata signals are used to retrieve data from the processor. The processor is asynchronously reset with the

Figure 3-1. High Level Description of MPLS Processor

reset signal. Both readdata and writedata are thirty-two bits wide, the address signal is four bits and all other signals are one bit wide. The processor interacts directly with the Avalon bus architecture described in [4]. The waitrequest signal indicates when the processor is performing a task. Consult Appendix A for a test bench illustrating how these signals are used to perform various tasks with the MPLS processor.

Table 3-1 describes how the address is interpreted depending on whether the user is reading or writing data. Data for LSPs, links, packet data and configuration are written while packet data, status information and labels are read. Full descriptions of the register formats associated with the addresses are provided later in this chapter when the relevant modules are discussed.

Figure 3-2 describes the format of the control register. Four bits are used for a command and five bits are used as an LSP reference when necessary. The LSP reference must correspond to the sequence of LSPs that has been entered with the numerical reference beginning at zero. Therefore, if the number three is put as the LSP reference then it will refer to the fourth LSP that was successfully saved.

Table 3-2 shows the formats and definitions for the user commands available in the control register. The input and output stack can be separately cleared as well as LSP module and the TE DB. Users can also create PATHTEAR or RESVTEAR packets on command, process a saved packet, establish LSPs (generate PATH packets given the network topology) and save various data types.

Table 3-1. MPLS Processor Address Values

Value Type of data Read/Write Description

0 LSP Write Destination address

1 LSP Write Source address

2 LSP Write Tunnel and LSP IDs

3 LSP Write Refresh rate

4 LSP Write Peak data rate

5 LSP Write QoS data (excluding peak data rate) 6 Link Write Next hop IP address

7 Link Write Bandwidth

8 Link Write Port IP address

9 Link/LSP Write Upstream, downstream, TE DB ports 10 Configuration Write Packet flags and initial TTL

11 Configuration Write Initial label

12 Packet Write Packet data

13 Configuration Write Control register

0 Packet Read Packet data

1 Status Read Status register

2 LSP Read Input label

3 LSP Read Output label

Others N/A N/A N/A

Figure 3-2. MPLS Processor Control Register

Figure 3-3 describes the components of the processor and their interaction. The high level logic module coordinates all other modules and the Avalon bus to satisfy all the processor’s requirements. Functions directly supported by the high level logic module are interaction with software, data entry and data removal. All connections to the high level logic module are not shown to clarify Figure 3-3. The following hardware components have also been developed for the processor: the packet parser, the packet generator, the error generator, the traffic engineering database, the label generator, the label database, the LSP module, and external data module.

Modules collectively used to satisfy the requirement of processing and generating the mandatory set of RSVP-TE packets are the packet parser, packet generator, error generator and label generator. The packet parser is used to process an entire packet,

Table 3-2. User Command Formats for Control Register

Value Command

0 Reset processor

1 Clear input stack 2 Clear output stack 3 Clear LSP data 4 Clear TE DB data

5 Create PATHTEAR packet 6 Create RESVTEAR packet

7 Process packet

8 Establish LSPs

9 Save LSP data 10 Save TE DB data

11 Save packet data

Others No command

separating all the individual components into addressable parts and checks for a predetermined set of errors. All packets are created with the packet generator given the type and various possible data sources. Those sources include every other component of the processor so the packet generator has logic to differentiate between the appropriate data source and value in forming a packet correctly. The error generator takes its inputs from the packet parser and sends an output to the packet generator to indicate if there is an error. Values sent to the packet generator are error codes documented in section 2.2.4. The label generator generates a previously unused number as a label. A subset of labels that are reserved according to the MPLS specifications. The first label that can be assigned is stored in the label generator.

All requirements relating to TE data are provided by the traffic engineering database (TE DB). The TE DB contains all information for the router’s bidirectional links. That information includes IP addresses, internal port identifiers, reserved bandwidth and remaining available bandwidth. It is also possible for a user to specify the percentage of total bandwidth that can be reserved per link.

The label database facilitates the requirements for storing, retrieving and updating label data. References are maintained for each LSP and its corresponding pair of labels. Those labels are for packets headed upstream and downstream on the LSP so the correct

Figure 3-3. High Level MPLS Design

value can be read by the user or switched into the packet depending on the direction of traffic.

Before data is directed to its appropriate module it is stored in an external data module, denoted ‘Config/LSP Info’ in Figure 3-3. Connections from this module to all other modules are not shown to simplify Figure 3-3. Information to configure the processor (i.e. router type, etc.) are processed by the high level logic module but not redirected to a separate module.

Chapter 4