Arrayed gate mesh electrode

The first device etched was an arrayed gate mesh electrode to match the 5x5 CNT cathode array chip. Normally a tungsten 100 mesh was used as the gate electrode for the 5 x 5 CNT cathode array. The mesh structure is made of wires interwoven at right angles so it does not present a perfectly flat surface over the cathode. Also it is a more flexible material and can deform or bow causing greater height discrepancies between adjacent cathodes. This was observed in one case with the mesh bowed down over one side of the cathodes possibly affecting the responses of the cathodes to the gate voltage. The silicon mesh structure allows one to form a much more uniform surface to place over the cathodes, and it is not as

susceptible to deformation. Similar devices have been etched using DRIE[1] but using somewhat different processes.

The wafer was etched first by KOH to a depth of 280 um and then via DRIE using the sputtered chromium etch mask. The pattern for the gate mesh is shown in Figure 5.2(a). The wafer was etched via DRIE for 15 min and removed. The etch depth was measured at an average value of 55 um, yielding an etch rate of just under ~3.7 um/min. The wafer was then etched for an additional 20 min and removed. Partial breakthrough of the silicon was

observed as seen in Figure 5.2(b). The wafer was then etched for several additional 3 min intervals to attempt to complete the etch.

(a) (b)

Figure 5.2: (a) 5x5 gate mesh array mask pattern and magnification of a the mesh for one pixel (inset image). (b) Optical microscope image of partially etched silicon layer from the backside of the chip, with holes near the edges not yet completely etched.

Each quadrant of the wafer contained a 5x5 gate mesh array (a 3x4 portion of the gate array is seen in Figure 5.3(a)), and some quadrants of the wafer saw nearly complete etching on each mesh. Others did not demonstrate complete etching because of process problems encountered. In order to avoid etchant attack on the wafer chuck with through wafer etching the wafer was mounted to a silicon backing wafer. Fomblin oil was used to provide adhesion between the device and backing wafer. When the etch broke through the silicon some of the Fomblin oil bubbled through open parts of the mesh and contaminated areas not yet

completely etched, effectively terminating the etch in those areas. And in another area of the wafer incomplete removal of contaminants blocked the etch. This accounts for some of the etch defects encountered. To overcome the problem of incomplete etching on successive runs Kapton tape was used to attach the wafers or wafer pieces to backing wafers in lieu of Fomblin oil. The Fomblin was used for its purportedly better thermal contact, but the Kapton tape provided a reasonable alternative.

Nevertheless some areas saw complete etching over the entire quadrant, resulting in a fully realized 5x5 array gate mesh electrode. Having etched away 280 um of Si thickness in the KOH a remaining silicon thickness of ~120 um was measured as seen in Figure 5.3(c), demonstrating strong process control using this method.

Because we were only able to perform this fabrication process once as a result of time constraints no optimization of the design of the silicon mesh was possible. However the structure represents the best first effort towards a custom gate structure. As mentioned the surface of this microfabricated mesh is extremely flat when compared with the tungsten mesh, and this provided one rationale for this method. In addition to this flatness the initial design attempted to maximize open area, achieve mechanical stability, and present a uniform

(a) (b), (c)

Figure 5.3: (a) SEM image overview of a 3x4 area of the 5x5 matrix of the gate mesh array. (b) SEM image of a tilted single gate mesh showing the area etched via KOH and a fully etched mesh. (c) Higher mag SEM image of the gate mesh tilted to show the sidewall of the etched holes; the depth is measured to be ~31.3 um with a tilt angle of 15°, the actual depth and the thickness of the remaining Si layer is 121 um.

electric field over the cathode. In this case the design values were for 20 um beams with 60 um square holes. Given certain process biases the final dimensions as measured by SEM were ~15 um beams and ~ 65 um square holes. The as drawn open area would have amounted to 56%, but after the process bias that value was increased to 66%. As for mechanical stability the mesh structure appears adequately rigid. None of the beams were observed to break, although given their short spans as compared with their thickness this would have been unlikely. As a precaution against beam breakage or cleaving the corner of the square holes were filleted. Finally the relatively small size of the squares along with the regularly spaced and even beams should provide for a more uniform electric field than the tungsten mesh used, although part of this is achieved via loss of open area and consequently potential loss of electron flux to the anode. Given the fabrication of these and other

components via DRIE near the end of the project field emission testing experiments were not completed. Nevertheless this technique demonstrates the capability of making custom mesh structures and patterns, which could be designed for special cathode shapes or cathode arrays in the future. Additionally custom patterns may be useful for optimizing electron beam focusing or transmission rates.