ASIC design

The purpose of this section is to help the board designer to specify custom ICs in an informed manner, so that they include features which will secure board testability. Failure to follow the requirements set out in this chapter could significantly reduce the testability of the finished board design.

7.4.1. Initialization

It must be possible to set the IC into a known state by application of a simple waveform at one or more inputs.

Ideally, the IC should be provided with a single asynchronous or synchronous reset input which, when the correct signal is applied, causes every part of the design to be set to a known state.

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If this is not achievable, then initialization must be achieved by an alternative means within the constraints specified in Section 8.2.

7.4.2. ASIC features needed to help in board test

Ability to force an inactive drive state at output pins

The IC must be designed such that all output pins can be set to a high-impedance or inactive drive state when an appropriate condition (input signal, instruction, and so on) is applied. Where this capability is not needed to meet functional requirements, then it must be provided solely for test purposes. It is essential that output pins can be placed in the high-impedance (inactive drive) state while in-circuit testing of adjacent components is in progress (see Chapter 1). Control of the facility can be achieved either through a dedicated test pin or through a specific instruction applied to the chip via an ANSI/IEEE Std 1149.1 Test Access Port (see Chapter 3).

ANSI/IEEE Std 1149.1

All ASIC designs should include design-for-test features in accordance with ANSI/IEEE Std 1149.1, Test Access Port and Boundary-Scan Architecture.

7.4.3. Test quality targets

A high quality test programme must be available for each custom IC.

Why is a high quality test needed?

Like printed circuit boards, custom integrated circuits must be tested to a sufficiently high standard following production to ensure an acceptable shipped quality level. The result of an inadequate test is that faults may remain undetected in components shipped for assembly onto a printed circuit board. Such 'dormant' faults may be detected either when the assembled board is tested or, in the worse case, may cause intermittent failure of a system in the field. Many companies have estimated that it costs 1000 times as much to locate and replace a faulty IC in the field as it would have cost to find the defect immediately following chip production.

What faults should the test detect?

The following fault types must be included in the target fault set:

(1) Stuck-at faults on device outputs. These faults represent device outputs becoming fixed at 0 or 1. Note also that the possibility of device outputs becoming stuck-at-Z (high impedance) should be

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considered for devices with 3-state or bidirectional pins, but may lead to 'potential' detection (see below) unless the design ensures that the bus is pulled to 0 or 1 when it is not driven from another source.

These faults all apply to a complete connection between devices — the fault is seen by all devices fed from the connection.

(2) Stuck-at faults on device inputs. These faults represent individual device inputs becoming stuck at 0 or 1. The faults only affect the specific input and not other devices driven from the connection. They model defects in the fan-out branches of an interconnection — for example, an open-circuit in the segment of track feeding one gate input. In some simulators these faults are simulated as stuck-at faults, while in others they are simulated as open-circuit faults where the disconnected side of the connection is coerced to 0 or 1.

Note that a 'device' may be a logic gate or more complex cell in a semi-custom IC, or a transistor in a full-semi-custom IC, depending on the level at which the circuit is modelled for simulation.

Optionally, the following class of faults may also be considered if time and budget permit:

(3) Bridging faults between adjacent device pins. These faults can be used to simulate solder shorts, etc. between adjacent terminals of a device or between adjacent tracks.

How many of the target faults should the test detect?

The target is for the test programme to allow all faults in the target fault list to be assigned into one of three categories, as discussed below. Under no circumstances should the number of faults which cannot be categorized exceed 5% of those in the target fault list.

A fault is deemed to have been detected by a test programme as a result of one of the following:

(1) 'Hard' detection. A hard detection occurs when a fault causes a change from 0 to 1 (or vice-versa) at one or more points monitored by the external test equipment.

(2) 'Potential' detection. Potential detection occurs when a fault causes a predefined number of changes from either 0 to X (unknown) or from 1 to X at one or more points monitored by the external test equipment. The number of observed changes before detection can be adjusted to change the confidence in the detection of the fault, since the observed unknown signal state could be the fault-free value or its complement. A figure of 5 observed changes to X is typical.

(3) Acceptable non-detection. There will typically be some faults for which detection is not possible due to the nature of the circuit design.

For example, where a circuit contains redundancy, not all faults will

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be detectable since correct operation of one part of the circuit will prevent the incorrect operation of another from causing failure at a point observable to the ATE. A further example would be a

stuck-at-1 fault on a device input which is tied to the logic stuck-at-1 since it is not required in the particular design. 'Acceptable non-detection' includes all cases where there is a clear reason why hard or potential detection is not possible.

A pitfall you should avoid

Normally, test quality will be verified using a fault simulator. However another technique — 'node toggling' — is sometimes advocated by silicon vendors or design houses. In the node toggling technique, a check is made on a simulation of a test programme to ensure that each connection (node) is at some point set to both 0 and 1. Clearly, if a node does not get set (say) to 0 then the test programme cannot detect stuck-at-1 faults. However, simply setting the node to both 0 and 1 is not sufficient to ensure, that faults on it are detected — the effect of the fault must also be made visible to the ATE at the component's outputs. Detection of the fault can only be guaranteed using fault simulation.

7.4.4. Internal testability

As for printed circuit boards, test costs for custom integrated circuits can be a significant part — sometimes as much as 50% even for relatively testable designs — of the total development cost, particularly for complex full-custom ICs. Clearly, costs of this magnitude can have a significant impact on the viability of using custom silicon in a product.

For this reason, it is recommended that highly-structured design-for-test techniques such as scan design and self-design-for-test are used wherever possible (see Chapter 2). These techniques can, in some cases, allow the test development task to be fully automated, thereby producing significant manpower savings. However, costs are incurred due to the need to dedicate a small number of package pins to test functions and due to increases in the physical size of the IC caused by test circuitry added to the design.

7.4.5. A typical testability budget for IC design

The amount which can be spent on design-for-test in an integrated circuit will depend on the quantity of devices which will be made over the production life. For high volume parts (such as microprocessors), test development costs per device are lower than for low volume parts (such as many semi-custom ASICs), so the amount which it is economical to spend on design-for-test is also lower.

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For a low volume part (say, up to 2000 for total production quantity), a typical budget would be:

O Additional circuitry — up to 15% increase in the number of gates.

O Additional pins — 5, to allow provision of ANSI/IEEE Std 1149.1.

(Note: Most test functions can be controlled through the interface defined by this standard.)

O Reduced performance — up to 5% of maximum operating speed.

For a high-volume part, the budgets for additional circuitry might be reduced to 5%. (Toshiba quote a variation between 20% for low-volume parts and 5% for high-volume parts within their company.)

Beware: if you do not allow an appropriate budget for testability (for example, the entire gate capacity is needed to achieve the system function) then you may eventually get an adequately tested component, but the cost will be high.

CHAPTER 8.