Assertion Generation

The arrival time customer framework can be used to generate assertions for the newly created ports. Let (A, κ) be a Steiner tree for a top-level net N that crosses at least one unit border. Let s be its source. Arrival time customers yield an arrival time at s: If s is a primary port, the arrival time at(s) is given with the instance. Otherwise, the source port is a unit’s output port and we can use the solution of the arrival time customers at the preceding input port plus the time it takes to propagate through the unit. Similarly, we obtain a required arrival time rat(t) at each sink t ∈ N\{s}.

Let s0

1, . . . , s0k be the points where (A, κ) crosses the source’s unit border if s is an

output port of a unit, and let s0

1 = s, k = 1 if s is a top-level port. For each sink t ∈ N\{s}

that is neither a top-level port nor an input port of the source’s unit let t0 _{be the point}

nearest to t where A[s,t]crosses the border of the unit to which t belongs. For sinks that will

not be moved during port assignment we set t0 _{:= t. We assign arrival times at(s}0

i) :=at(s)

for i = 1, . . . , k and at(t0_{) :=rat(t) to the sinks. By propagating the linear delay values}

ρ(e) from the s0_i along (A, κ) in topological ordering, we can define arrival times at(v) at the other points v where (A, κ) crosses unit borders. These values serve as assertions for arrival times and required arrival times for the corresponding ports.

Together with the delay-per-length values that define the values ρ(e), Bartoschek et al. [Bar+10] compute default capacitances and slews for given layers and wire codes. At input ports these values can be used as assertions for capacitance limits and output slew.

At output ports they can be used as assertions for slew limit and capacitance. Let t ∈ N\{s} and let s0 _{∈ {s}0

1, . . . , s0k} such that t0 is reachable from s0 in A. One

can think of several improvements to refine assertions depending on the slack wsl(t0_{) :=}

at(t0_{) −at(s}0_{) −linear_delay}

(A,κ)(s0, t0).

Distributing positive slacks. In case of positive slack on a path we distribute the slack to all units. We compute a delay scaling factor α > 1 such that maxt∈N \{s}{wsl(t0)}

becomes zero if we increase all delays by a factor of α. It is also possible to scale delays non-uniformly.

Distributing negative slacks. In case of negative slacks, we distribute the slack be- tween source and sink units. In all other units, and for top-level connections, negative slack is usually unwanted. To accomplish this, we increase at(t0_{) by −}wsl(t0)

2 for all

t ∈ N \{s} with wsl(t0) < 0. For i = 1, . . . , k we decrease at(s0_i) by 1₂ · max{−wsl(t0) : treachable from s0_i in A}. This method can be refined further by distributing the negative slack non-uniformly between the source and the sink continent.

Improved assertions by buffered Steiner trees. Instead of computing assertions based on the linear delay model, we can directly compute buffered Steiner trees. Instead of using default values for capacitance and slew, we can propagate the actual slews, slew limits, capacitances and capacitance limits along the fully buffered Steiner tree and obtain more accurate assertions. When computing these buffered Steiner trees it is important that these are electrically correct and have a good timing with respect to a delay model that measures slew effects. Buffered Steiner trees computed with the algorithms presented in Chapter 4 do not fulfill these requirements. In Chapter 7 we show how to compute a low-cost buffering of a given Steiner tree. In addition to routing and placement congestion, these costs model penalties for capacitance and slew violations, and for slew-dependent delays.

The methods described in this section are not only of theoretical interest but are actually used in practice at IBM. An example output of a real-world top-level design for which ports and assertions have been created as described are shown in Figure 6.11.

(a) Top-level view on the design. Each unit is plotted in a different color. The top-level routing is not shown.

(b) Zoom into the top-level routing shows distribution of the wires that define ports.

(c) Zoom into Figure 6.11(b) shows created ports (white boxes).

Figure 6.11: Real-world output of port assignment. Pictures are shown in 2-dimensions although the used global routing graph is a 3-dimensional graph.

Buffering a Given Steiner Tree

Buffering algorithms in today’s physical design flows typically work in two steps. 1. In a first step a Steiner tree or a topology is computed.

2. This Steiner tree or topology is then buffered.

Since we already discussed algorithms for the computation of topologies (Chapter 5) and Steiner trees (Chapter 6) in previous chapters, we concentrate on the second step in this chapter. As before we try to minimize costs for delays, routing congestion, placement congestion, and other costs including costs for net length and power. We also try to obey capacitance limits and slew limits.

After having recalled existing buffering algorithms (Section 7.2) we will introduce a new approach to realize Step 2. This algorithm unites classical dynamic programming algorithms (e. g. Van Ginneken [Van90]) with the Fast Buffering Algorithm by Bartoschek [Bar14] and Bartoschek et al. [Bar+09]. We discuss two versions of it. In a basic version we propagate many candidates and obtain good solutions. We show how to make use of information based on repeater library and input characteristics to prune most candidates without degrading the results too much. We obtain a fast mode of our algorithm that can be used even for large designs.

After the bicriteria algorithm of Section 5.3 to compute a routing topology and the topology-embedding algorithm contained in the proof of Theorem 6.2, the algorithm presented in this chapter is the last building block of a (heuristic) buffering-and-routing oracle that can be used in the resource-sharing-based timing-constrained global routing framework introduced in Chapter 3. This oracle will be fast enough for practical application.

7.1

The Minimum Cost Steiner Tree Buffering Problem

In this section we give a detailed formulation for the Minimum Cost Steiner Tree Buffering Problem. Since this chapter is targeted at improving results on practical VLSI instances we have to make several deviations from the setting in the previous chapters. In particular, we no longer make use of the simple version of Elmore Delay model ([Elm48]) described in Section 4.2.1 that does not consider slew effects.