ATPG Algorithm for Crosstalk Delay Faults

3.3.1

Basic Idea of Algorithm

In dealing with high-speed interconnection circuits, the algorithm proposed in this paper, which represents an improvement over the traditional FAN algorithm [7], analyzes the four classes of crosstalk delay fault in high-speed interconnection circuits with the maximum aggressive model and waveform sensitization technol- ogy. In consideration of gate delay information and line delay information, two strategies, static priority and dynamic priority, are studied in search of an ATPG algorithm of test vectors with the time parameter for the test fault.

3.3.2

Generation Process of Test Vector of Algorithm

After a fault target is selected, the aggressive line is activated by the largest delay. In the generation of a test vector, this paper discusses two test vector generation strategies and makes certain improvements over the FAN algorithm according to the characteristics of the crosstalk fault. Figure3.1shows a flow chart of the test vector generation algorithm. The full process of test vector generation mainly includes three phases: sensitization of the victim line, determination of circuit timing information, and the course of test vector generation with the time parameter.

The steps of the flow chart for the test vector generation algorithm are as follows.

3.3.2.1 Sensitization of Victim Line

First, in the course of analyzing a test circuit, a random line is chosen from the test circuit as the fault line with the corresponding maximum aggressive assembly 3 ATPG Algorithm for Crosstalk Delay Faults of High-Speed Interconnection Circuits 21

found as well; then the fault border of the fault line is determined from the test circuit to form a fault border assembly; finally, the specified fault for the fault line is chosen from the four fault types: rising delay accelerated failure RI, rising delay reduction failure RD, falling delay accelerated failure FI, and falling delay slow fault FD.

3.3.2.2 Determination the Circuit Timing Information

Then, when the delay information of the test circuit has been obtained, the delay information is added to the circuit being tested. First, a static timing analysis of the gate-level net table generated from the test circuit is conducted, which yields information about the circuit line delay and gate delay. Then, both the fault line time and the aggressive line signal time are assumed to beT.

3.3.2.3 Test Vector Generation Process with Time

After the victim line is sensitized and the circuit timing information obtained, the process of generating a test vector with time is conducted, and the steps are as follows:

Fig. 3.1 Flow chart of test vector generation algorithm

1. Depending on the fault type of the fault line, first, obtain the jump information on the aggressive line to determine the assignment of the aggressive line; then determine the assignment of all other input lines, in addition to the fault line on the fault border closest to the original output; finally, insert the assignment line directly into the goal assembly using a dynamic priority strategy.

2. Check whether the current target set is empty; if so, go to step (3); if not, to remove a line in the set, delete it from the set and check whether the selected line is the fan outlet. If so, add it to the fan outlet target set; if not, then check whether the line is the original input line. If it is, put it in the backcourt target assembly; if neither, then you are dealing with a pushback process, that is, immediately push back a gate and subtract the gate delay of the logic gate and the line delay passing the lines in case of the current time valueT. Repeat step (2) for the pushed-back line. If it still does not satisfy the requirements of the fan outlet line and the input line, keep passing the next gate and push back in the next line until it satisfies step (3).

3. Check whether the fan-out target set is empty; if so, go to step (4); if not, take the fan-out line closest to the original outlet as a target and delete it from the fan outlet target. First, check whether the chosen fan-out line has two or more assignment requirements, if it has only one assignment requirement, the line shall be pushed back following step (2); if there are two or more assignment requirements, make a judgment for each assignment of the fan-out line; take a value and make the validation according to the forward and reverse direction- containing process. If the fault boundary does not change, disappear, or come into the state which contains contradiction, then the value is feasible and thus taken as the value of the outlet; then, continue pushing back with step (2). If the fault boundary does change, disappear, or come into the contain contradiction, the value is not feasible.

4. Finally, check whether the fault line is the original output line; if so, that means the fault has spread to the original output and the fault signal can be sampled after the sampling timetis determined. With the identified assignments of each line, obtain the remaining nonverified lines through the backward and forward contain in the test circuit using the static priority strategy to obtain the test vector with a time coefficient; if the fault line is not the original output line, then spread the fault forward to the next logic gate through the current one, and add the gate delay of the logic gate and line delay of the passed line to the current time value

T. The fault boundary will change at the time, while there is no need to determine the jump information of the aggressive line. Repeat the entire test vector generation process starting with step (1). Spread the fault forward to the original output line step by step, and then determine the remaining nonverified lines in the test circuit; finally, a test vector with time can be obtained.