The task of the ATC is color management. It's the second highest authority in a VGA card. Using this controller is somewhat more complicated than the others since only one port is available for write access. An index/data flip-flop occurs at 3c0h, i.e., this port alternates with each write access between index modes and data modes.
You can set the initial status of this register explicitly to index mode through a read access on Input Status Register 1 (Port 3dah in color mode, 3bah in monochrome mode). A write access is then performed. First, the index is written to 3c0h. This is followed on the same port by the data byte which is followed again by the next index.
The read access is somewhat different. After the index has been written, the data byte can be read using Port 3c1h. Here a read access on 3c0h would return the index.
Another unusual feature is the structure of the Index/Data Register at Port 3c0h. Bits 4-0 as usual give the index. However, Bit 5 has a broader meaning:
ATC-Register: Index/Data Port 3c0h
Bit Meaning Access
7-6 Reserved RW
5 Palette-RAM access RW
4-0 ATC index RW
Explanation
Bit 5
A value of 0 enables CPU-access to the palette-RAM (Registers 0-f), yet disconnects the ATC so the image is set to the frame color. You should always reset this bit to 1 after any changes.
Bits 4-0
Give the index on an internal ATC register. This value is then written using Port 3c0h, and read using Port 3c1h.
ATC-Registers 0-f: Palette RAM
Bit Meaning Access
7-0 DAC color RW
Explanation
Bit 7
These registers are used to supply all EGA color values with the actual colors. The red, green and blue values in EGA have been stored here directly. However, the Digital to Analog Converter (DAC) in VGA acts as an interface. The DAC's first 16 palette entries simulate the same color scheme. Here, for example, you can set text colors to new DAC values.
ATC-Register 10h: Mode Control
Bit Meaning Access
7 Source for Color Circuits 4 and 5 RW
6 PelClock / 2 RW
5 Enable pixel panning RW
4 Reserved
3 Blinking on RW
2 Line graphics enabled RW
1 Monochrome- (1) / color (0) attributes RW
0 Graphic (1)/ text (0) RW
Explanation
Bit 7
In graphic modes with 16 or fewer colors this bit determines the source for Color Circuits 4 and 5. A 1 means these bits are taken from Bits 0 and 1 of Register 14 (Color Select). A 0 will load the lines with palette register values. When using the Color Select method you can shift the DAC palette area in blocks of 16. This also applies of course to EGA mode and CGA mode.
Bit 6
A 1 halves the speed at which pixel data are sent to the DAC. This finds application in 320 x 200 x 256 mode, since here only half the horizontal resolution is used.
Bit 5
A 1 prevents pixel panning below the split-line, a 0 causes panning over the entire screen.
Bit 3
A cleared bit enables use of all 16 ATC palette colors. A 1 enables blinking. When this bit is set, the top and bottom halves of the palette in the Intensity Plane alternate continuously. This happens in both text mode and graphic mode so only eight colors are available. The advantage is the palette can be freely constructed, enabling almost any type of blinking effect.
Bit 2
A 1 doubles the eighth column of characters in 9-pixel text modes (e.g. Mode 3) with ASCII codes between 0c0h and 0dfh. This allows line characters to be connected without gaps. With a 0 in this bit, the ninth column is cleared or acquired from the Intensity Plane (Plane 3).
Bit 1
Bit 0
A 1 switches the ATC to graphic mode, a 0 to text mode.
ATC-Register: Index/Data Port 3c0h
Bit Meaning Access
7-6 Reserved RW
5 Palette-RAM access RW
4-0 ATC index RW
Explanation
Bits 7-0
Determine the color number used in the overscan area. This is also where EGA cards with a 6-bit RGB value entered. Color mixing with VGA occurs using the DAC.
ATC-Register 12h: Color Plane Enable
Bit Meaning Access
7-6 Reserved RW
5-4 Reserved, often test bit configuration RW 3-0 Enable plane
Explanation
Bits 3-0
Enable (1) and disable (0) the corresponding plane, excluding from the display specific color components (16-color models) or specific pixels (256-color models).
ATC-Register 13h: Horizontal Pixel Panning
Bit Meaning Access
7-4 Reserved RW
3-0 Horizontal pixel panning RW
Explanation
Bits 3-0
Specifies the number of pixels by which the entire image (text- or graphic mode) is shifted to the left. The actual values, however, are somewhat different. The value 8 In 9-pixel modes indicates that no shift will take place. Values from 0-7 create shifts of 1-8 pixels. This makes little sense in graphic modes since you might
as well work with the start-address. In text mode however this will allow very smooth scrolling (see Chapter 5).
ATC-Register 14h: Color Select
Bit Meaning Access
7-4 Reserved
3-2 Color Circuit 7-6 RW
1-0 Color Circuit 5-4 RW
Explanation
Bits 3-2
In graphic modes with fewer than 256 colors, these bits give the upper two bits of each color value sent to the DAC. By reprogramming this register you can move the 16 EGA colors to Palette Offsets 0, 64, 128 and 192.
Bits 1-0
If Bit 7 is set in Mode Control Register 10h, in graphic modes with fewer than 256 colors these two bits set Color-Bits 5 and 4. In combination with Bits 3-2, EGA colors can then be moved to any color offset divisible by 16.