Automatic Test Pattern Generation

ATPG tools have been a great benefit to test engineers. Since they take advantage of structural fault models to generate patterns, the same tool can be used in many different designs with very different architectures. These tools are widely available to industry whether it is commercially [10] or from academia.

The goal of these tools is to deterministically generate patterns that will stimulate a fault site and propagate the potential fault effect to an observation point to identify as many faults as possible with as few patterns as possible. While not all faults will be

testable due to the topology of the circuit, the ATPG will be able to generate patterns for those faults that are testable. The ability to test these fault sites is measured by the fault coverage, which is a fraction of the number of faults detected after pattern generation over the total number of faults in the design, as shown in Equation 1.1, where FC is the fault coverage percentage, DT is the total number of detected faults, and TF is the total number of faults in the design. There is additionally another metric often used by these tools called test coverage. The test coverage, as calculated in Equation 1.2 considers those faults that are not testable either due to circuit redundancies or tied off signals that would make coverage of particular fault types impossible. TC is the test coverage percentage and UT are those faults that have been classified by the ATPG as untestable.

F C = DT

T F × 100 (1.1)

T C = DT

T F − UT × 100 (1.2)

While the fault coverage provides a metric of how much of the design has been covered with the generated pattern set, the test coverage essentially measures the effectiveness of the ATPG tool. These two values can also be used to help guide design issues since a large discrepancy between the two values could imply a potential problem in the design. While each commercial vendor has their own proprietary algorithm for pattern and coverage optimizations, they all basically follow a similar flow as shown in Figure.1.2. First, a fault dictionary for the design has to be built. Next, the tools begin to deter- ministically target these faults one at a time. While the patterns are being generated, compaction of the patterns also occurs dynamically. This is possible since very few bits of the pattern are usually needed to stimulate and observe a specific fault site. After the pattern generation and compaction have filled in some of the pattern’s with care-bits, the remaining don’t care bits can be filled randomly or with some other fill scheme. The final fully specified pattern is then fault simulated for any fortuitous detection of additional faults.

The automatic test pattern generation (ATPG) is the process of automatically gen- erating a set of test patterns for detecting a specific group of faults. The inputs of the ATPG procedure are design data (e.g., netlist), fault group (specifying what faults are

Design Fill Don't-Care Bits Fault Simulate More Fault in List? Yes No Build fault list Pattern Generation and Compaction Select Fault Generated Pattern set

Figure 1.2: General ATPG Flow

targeted), test protocol and test constraints, and the output is a set of test patterns. The test patterns are then applied to the design for fault detection. If a fault can be detected by the input test patterns, it is called as a detected fault. Otherwise, it is an undetected fault. Note that there may be some faults in the design that cannot be detected by structural patterns, which are called undetectable faults.

ATPG algorithms inject a fault into the CUT, and then use a variety of mechanisms to activate the fault and propagate its effect to the circuit output. The output signal changes from the value expected for the fault-free circuit, and this causes the fault to be detected. There are various ATPG algorithms that can be found in the literature. Some of them are listed below:

• Roth’s D-Algorithm (D-ALG) [75]; • Goel’s PODEM algorithm [76];

• Fujiwara and Shimono’s FAN algorithm [77];

• Schulz’s learning ATPG programs SOCRATES [79] [80][81]; • Giraldi and Bushnell´s EST methodology [82] [83][84];

• Kunz and Pradhan’s Recursive Learning methodology [85] [86][87]; • Chakradhar’s NNATPG algorithm family [88];

• BDD-Based ATPG Algorithms [89][90].

The following terms are important test generation definitions and are commonly used in ATPG literature:

• Controllability: A testability metric that measures how difficult it is to drive a node to a specific value.

• Observability: A testability metric that measures how difficult it is to propagate the value on a node to the primary output or scan flip-flop.

• Sensitization: The process of sensitizing the circuit and enable the fault to cause an actual erroneous value at the point of the fault.

• Propagation: The process of propagating error effects to the primary output or scan flip-flop.

• Justification: The process of finding the input combination required to drive an internal circuit node to a specified value.

All the above terms in this section are utilized in the coming chapters during the explanation of our methods to generate patterns.