Avalon SoPC Components

This section is a brief overview of the standard Avalon components used in the system and focus is on the more interesting high-level components. Note: lower case names are system components.

The NIOS II Processor: this is a 32-bit Harvard-architecture RISC processor that can address 2 Gbytes of space [64]. It can be instantiated in three versions. The version used for this thesis is the NIOS II/e with a minimum feature set.

The user sets the reset vector and exception vector. The processor also comes with a joint test action group (JTAG) debug port [65]. The full version of the NIOS II incorporates more advanced features such as a hardware multiplication unit, configurable instruction and data caches, configurable interrupt controller, and configurable memory management support.

There are three total NIOS II/e processors in the system. The Security Controller uses a NIOS II for command and control (nios2_qsys_0). Its data bus is

connected to the local RAM, Security Bridge, Security RAM, the user RAM, the SD card via a Parallel Input/Output (PIO) interface [42], a Universal

Asynchronous Receiver/Transmitter (UART) [42] for user interaction, a reset controller that controls the user Nios II reset, LEDs, switches, the user UART, and finally, PIO used to program the User FPGA. Its instruction bus is connected to the same local RAM.

The second is the user Nios II (nios2_qsys_1). Its data bus is connected to a local RAM for fast, unencumbered access to data and is also connected to the User Bridge so that it can access the full system. The instruction bus is

connected to the local RAM and also to the User Bridge so that it can execute code from user RAM. It has a second connection to the User Bridge that allows it to configure the bridge.

The third Nios II appears on the User FPGA as an example configuration. Refer to Figure 1.

Clock Source (clk_0): this SoPC component takes an actual clock input and redistributes it along with a reset to every component in the system.

Altpll (alt_pll_0): this component is a configurable PLL used to condition the system clock such that it is advanced by 10 ns for use with the SDRAM. JTAG UART: this is a UART to JTAG interface that allows the system to communicate with a terminal window. There are multiple ones in the system. Jtag_uart_0 is connected to the data bus of the Security Controller NIOS II and is used to communicate with the user and to get the pass key password.

Jtag_uart_1 is connected directly to the user NIOS II, is inserted for development only, and would not be used in a full system. Uart is a JTAG UART connected to the Security Controller data bus and can be accessed by the user Nios II

according to the security policy. Ghost_uart is a JTAG UART connected to the data bus of the user Nios II and is in place as a software construct. For a system developed as Case 1 in Figure 1, it is necessary for the Eclipse complier board support package to recognize and understand that a UART is present on the data bus. The User Bridge prevents the tool from seeing the UART attached to the Security Controller, so it does not allow for its use. For development

purposes, the ghost_uart could be addressed at the same location so that the Eclipse tool can compile for it.

RAM: there are multiple RAMs in the system design. Ram_0 is the Security Controller Nios II RAM and is initialized with the Security Controller program when the Security Controller FPGA is initialized. It is located on the data and instruction buses of the Security Controller Nios II. Ram_1 is the local RAM for the user Nios II. It is located on the instruction and data buses of the user Nios II. It can be initialized according to the user application needs. It can be configured to contain all of the user code, obviating the need for the user RAM that is mediated through the Security Controller. For this thesis, the user application is specified to run in the user RAM through the Security Controller. Ram is located on the Security Controller data bus and is accessible by the user Nios II as allowed by the access policy.

Parallel Input/Output (PIO): The Avalon PIO component allows for general- purpose input and output. The following is a list of PIO controllers that are connected to the Security Controller Nios II data bus: sd_data, sd_command, and sd_clock drive the SD card. Being PIO, the SD interface is in software. Additionally, ps_dclk, ps_d0, ps_nconfig, and ps_nstatus are command and status lines to the User FPGA to configure it and confirm that it is configured. The configuration protocol is designed in software to follow the passive-serial

programming option for the User FPGA. Other PIO connections to the Security Controller data bus are switches and LEDs. These interface to the switches and green LEDs on the DE2 board and make them software addressable.

SDRAM: The Avalon component labeled sdram is an Avalon-based SDRAM controller and connects to the SDRAM on the DE2 Board. The SDRAM is not

used in this thesis. Although the hardware functioned, the Avalon intellectual property SDRAM module would not properly process the data for converting its 16-bit contents to a 32-bit word in this system.