Basic Architecture characteristics

In document MULCORS-UseofMULticore procesorsinairbornesystems (Page 44-49)

MULCORS EASA Architecture – Characteristics

AIRBORNE SOFTWARE

9.3. MULTI-CORE TECHNOLOGY STATE-OF-THE-ART This chapter covers tasks 1 and

9.3.3. Basic Architecture characteristics

We can find diverse Multi-core processor architecture regarding the organization of cores on one hand and the different types of memory accesses on the other hand which is as most important as the organization of the cores.

The architecture for memory accesses can generate a lot of difficulties that we have to analyze and mastered before declaring that the processor can be used in a safe environment like an aircraft.

Three main processor family Architectures can be found in the market

 Unified Memory Access (UMA),

 Distributed Architecture (DA)

 Single Address space, Distributed Memory (SADM)

When analyzing market processor architecture, we can notice that GPUs from ATI or NVDIA for example have their main architecture based on the DA one with a variant that is each dedicated core memory is embedded in the chip.

This architecture consumes a lot of pins linked to Memory Independence per core so they are used for small core or for embedded cores  this family is not addressed in this report.

UMA multi-core processor architecture is organized around one memory which is shared between all cores (see chapter 9.3.3.1..1), this architecture can be found for example in Freescale and ARM family for their low-end processors.

SADM multi-core processor architecture is organized around Cores having their own cache, dedicated memory and can have accesses to other core memories using bus and/or Network. This architecture can be found, for example, in Freescale, ARM or INTEL® family for their high-end processors.

Example of deployed multi-core architecture:

UMA DA SADM

Freescale P1, P2 family NVIDIA, ATI Freescale P3, P4, P5 and T family

ARM CORTEX® A8 and below ARM CORTEX® A9,

CORTEX® A15

INTEL® Core I7, Core I5

Analyzing processors architecture, we can’t find show stoppers or unsuitable features that can be demonstrated at this level of abstraction.

That means that we need to conduct the analyze processor by processor, to verify if the corresponding architecture and associated features can be considered as suitable or not, so this is why Thales has moved to a generic approach based on criteria per domain:

 Interconnect

 Cache

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9.3.3.1. Memory sharing architecture

In this chapter we propose to present the different types of memory accesses and the key points associated with these architectures.

Unified Memory Access (UMA) 9.3.3.1..1

The multi-core processor architecture is organized around one memory which is shared between all cores:

In this type of architecture, Access time to the memory is the same for each processor but we can notice that this access time is directly linked with the memory bandwidth throughput; Read or Write operation performed from or to the memory can be only one data per access.

This type of architecture requires arbitration management on one hand and integrity mechanisms on the other hand to manage communication between cores and synchronization if required.

BUS Core 1 Core 2 Core n EXTERNAL MEMORY

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What about caches? 9.3.3.1..2

UMA architecture is upgraded introducing cache memories; these are high speed memories between cores and External Memory. These memories have the same class of access time as its dedicated core.

These cache memories introduce other kind of problems linked to data integrity. If two cores share the same data area, when one of these two manipulate a data item, the second core which has a copy of this data needs to know that the data item is upgraded by another core (this problem occurs mainly in SMP13 mode where one Operating System manages all cores allocating them to processes for one running Airborne Software application in a given period of time).

In multi-core processors we need to take care about how Cache Memory Coherency is assumed

13

SMP : Symmetrical Multi Programming

BUS Core 1 Core 2 Core n EXTERNAL MEMORY

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Distributed Architecture (DA) 9.3.3.1..3

In this Architecture, each core has the use of a dedicated memory with or without dedicated cache depending on the processor architecture.

A local network realizes the link between cores and it is used for data and/or command transfer

We can find the use of this kind of architecture, with or without caches, mainly in GPUs14 with a variant where memory is embedded inside the die and dedicated per core. A Network is used to communicate between cores and the outside.

Cores can be allowed (depending on the implemented policy) to have access directly to the data using the network. With this kind of architecture, the performance of the global processor is directly linked to the quality and performance of the local network. We can also speak about this being shared memory architecture.

Remark: in this architecture, Memory Cache Management is simplified and occurs in the same way as in a single core processor (separate cache and memory are dedicated to each core).

EXT MEMORY Core 1 Cache I/F EXT MEMORY Core 2 Cache I/F EXT MEMORY Core n Cache I/F LOCAL NETWORK

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Architecture named “Single Address space, Distributed Memory” or SADM 9.3.3.1..4

This is the last class of processor architecture named SADM where Cores have their own cache, they can also have dedicated memory but they can have access to other core memories using the bus or the Network.

In this architecture we can notice that we have separate clusters. Each cluster can have its own private memory shared between cores allocated to this cluster. Exchanges between clusters are realized using local Network.

Note: In some multi-core architecture, like in QorIQ™ from Freescale or in ARM, the cluster bus is also part of the global network. In this variant of architecture, the bandwidth is at least dimensioned to sustain all the transfers in a cluster without causing perturbation to the others (this point has to be verified when the selection of a multi-core is proposed).

EXT MEMORY Core 1 Cache BUS EXT MEMORY Core n LOCAL NETWORK Core 2 Cache Cache Core 1 BUS Core n Core 2 Cache Cache Cache

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In document MULCORS-UseofMULticore procesorsinairbornesystems (Page 44-49)