Basic Concept of 3-Dimensional Packaging and Integration Technology

3D integration and packaging technology is without question the hottest topic in microelectronics today. An effective solution for integrating similar or dissimilar chip had been released by employing this technology. At the same time, it was an emerging technology that can form highly integrated systems by vertically stacking and connecting various materials, technologies and functional components together (J.Q. Lu et al, 2007).

Traditionally, CMOS technology was designed based on 2-dimensional (2D) planar architecture and integrated into a single layer of die. Each die is individual assembled and placed on a planar interconnect substrate, mainly printed circuit board (PCB) to form a complete system (E. Beyne, 2006). Moreover, it also provides a

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mechanical support and interconnection between different dies and components.

However, this technology is suffered on the system size, input/output (IO) density, and interconnects of the channel length due to the limitation of its physical structure. By using this 2D technology, the area-package efficiency (die to package ratio) is typically low (P. Asimakopoulos, 2011). Besides that, the signal is easily distorted when it travel through the long interconnect channel length which is lossy in nature. This is because the long interconnect channel length will lead to higher wire parasitic and propagation delay.

Unlike 2D planar architecture, 3D integration provides more motivation and benefits in order to meet the end user demands which included high functionality, small form factor and high performance. A 3D integration of integrated circuit is defined as multiple dies are stacked, vertically interconnected and integrated on a share common package (J. U. Knickerbocker, P. S. Andry, B. Dang, et al., 2008). The signal and power of the stacked dies are travelled vertically to device strata through short interconnect like flip chip, and TSVs. The innovation of the third dimension is using multiple layers of silicon substrate to arrange in a stacked configuration in which each layer containing transistors with different functionality. Similar to the conventional chips, the interconnect routing covered the planar surface of the each substrate, but also tunnel directly through layers in a vertical as shown in Figure 2.1.

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Figure 2.1: General view and outlook of through silicon via (TSV) and 3D integration (E. Beyne, 2006).

The significant advantages of 3D integration compared to 2D planar architecture are providing power efficiency, increased bandwidth interconnection and reduced latency operation (J. U. Knickerbocker et al, 2008). Generally, the length of the interconnect channel or wire is directly proportional to the global interconnect delay and power dissipation. Figure 2.2 shows 3D integration provides shorter interconnect channel length compared to 2D integration due to the flexibility of its stacked configuration. Instead of make a long route in 2D planar circuit, 3D integration provide shorter channel length by vertically connect 2 different dies. Hence, the total interconnect channel length is reduced and lead to the improvement of interconnect delay and power dissipation of the device.

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Figure 2.2: Channel length interconnection comparison between 2D integration and 3D integration (P. Asimakopoulos, 2011).

In general, there were three major types of 3D stack technology were emerged, wire-bonded chip stacks, package on package, and package in package. Although these approaches offer flexibility on known good dies testing, it caused long interconnection length and limitation on the interconnection among chips. There were few under development approaches for the chip stacking technology, chip to chip stacking, chip to wafer stacking and wafer to wafer stacking. Each of the approaches has their own benefits and limitations. High precision flip chip bonding is the common way to perform chip to chip and chip to wafer integration. Often, the die sizes will be different and heavily depend on their functionality and the density. For example, die sizes of a high density flash memory is different sizing with a low density flash memory or a normal microcontroller. Thus, these approaches are suitable to stack multiple known good dies in layers (C. Scheiring et al, 2004). However, these approaches are time consuming especially when the chips are bonded as arrays on a wafer. This is because the process has to be repeated as many times as the number of laminated chips in the array and if precise alignment accuracy is required, the process time for stacking each

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layer increases further (T. Fukushima et al, 2007). As a result, these approaches will lead to higher cost due to the low throughput at the fabrication side. In another said, these technologies can be used when high yield or dies of different sizes are needed for 3D integration (K. Sakuma et al, 2008).

In the other hand, wafer-to-wafer integration technology may provide an ultimate solution for the highest manufacturing throughput if high yield and a minimal loss of good dies and wafers can be realized (R. J. Gutmann et al, 2004). By applying this technology, it had to rise up the current production yield as much as possible.

Moreover, it required a strict control on the diameter size of the wafer so that each layers can be aligned with minimal tolerance. As a result, this causes the material and geometries become complex to handle due to the mismatches of thermal gradients between stacked wafers that lead to the displacement during their bonding process. The total yield of 3D integration using wafer to wafer technology is determined by multiplying the yield of each wafer in the stack (E. Beyne, 2006). Therefore, when the number of stacked layers increases, the compound chip yield will decrease exponentially. However, this technology could be applied with the high yield of known good dies per wafer.

13 2.1.1 Solder Bump Interconnection

Solder bumps are small spheres of solder (solder balls) that are bonded to contact areas or pads of semiconductor devices and that are subsequently used for face-down bonding. The length of the electrical connections between the chip and the substrate can be minimized by (a) placing solder bumps on the die, (b) flipping the die over, (c) aligning the solder bumps with the contact pads on the substrate, and (d)re-flowing the solder balls in a furnace to establish the bonding between the die and the substrate. This method provides electrical connections with minute parasitic inductances and capacitances. In addition, the contact pads are distributed over the entire chip surface rather than being confined to the periphery. As a result, the silicon area is used more efficiently, the maximum number of interconnects is increased, and signal interconnections are shortened. (Zheng Xu et al, 2009) shows the magnitude and phase of S11 and S21 using the inherent adaptive solving approach of Momentum for the solder bump interconnection model. The performance degrades as the frequency increases: reflection noises increases and signal gain reduces. At frequencies of 15 GHz, 20 GHz, 25 GHz and 30 GHz, the S11 are -31.02dB, -21.17dB, -14.82dB, -9.01dB respectively. On the other hand, the S21 are 0.34dB, -0.49dB, -0.73dB, and -1.51dB for the frequency of 15 GHz, 20 GHz, 25 GHz and 30 GHz respectively. By using the de-embedding and extrapolation method, the de-embedded results for both S11 and S21 on this technology are -6.13dB and -1.92dB for operating frequency at 45GHz.

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2.1.2 Surface Activated Bonding Interconnection

Surface activated bonding (SAB) was a recently developed high density interconnection method for advanced microelectronic system. SAB bonding was proposed based on the simple principle that two surface activated materials could be easily bonded together at the room temperature or low temperature. The surfaces were activated by fast atom beam or plasma irradiation source which has been proved helpful to remove the oxide and organic layer covering on the material surface (Zhonghua Xu, 2005). As bonding is carried out at the room temperature or low temperature and the material is surface activated before, no intermediate layer or impurity particle will exist at the as-bonded interface. That, for the SAB bonded Au-Al sample, a homogeneous intermetallic compound layer was finally grown and formed at the Au-Al interface (Au-Al) without any voids after 500hours thermal aging at 423K in air, which was completely different from the performance of Au-Al interface constructed by other interconnection techniques such as wire bonding or soldering flip chip method (Zhonghua Xu, 2005). (ChiTsung Chiu et al, 2002) shows the S11 and S21 are -12.78dB and -1.24dB respectively at 25GHz operating frequency. At 45GHz, the de-embedded result for S11 is -8.36dB and S21 is -1.35dB.

2.1.3 Through Silicon Via (TSV) Interconnection

As abovementioned (2.1), there were some limitations on the current emerged 3D stack technology. Thus, in order to overcome these problems, 3D chip-stacking

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technology using through silicon vias (TSVs) is investigated because it offers a way to solve interconnection problems by replacing the wire-bonded technology while also offering integrated functions for higher performance (M. Koyanagi et al, 1998). Besides that, it allows the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies (K. Sakuma et al, 2008).

3D integration TSV technology describes the process of vertically connecting several chips to achieve high functionality-to-volume ratio. In this technology, two or more vertically stacked chips are joined together by vertical interconnects running through the stack and functioning as components of the integrated circuit using established silicon technology (S. W. Yoon et al, 2009). The process sequence is different in TSV application, depending on either via first or via last formation approach is applied. However, the general process steps of TSV technology are bonding, thinning, wafer processing on bonded/thinned wafers, and subsequent de-bonding. The only different between these 2 process is via are etched during front-end-of-line for via first and back-end-of-line for via last. Via first process is favored by logic supplier and this is the most challenging process by far. The smallest via diameters for via-first schemes tend to be 5 to 10µm; aspect ratios are higher (10:1), posing challenges for liner and barrier step coverage, and for the quality of copper fill. On the other hand, via last approach is used in image sensors and stacked DRAM. CMOS image sensors have via diameters exceeding 40µm with aspect ratios of 2:1. In other devices, the vias range from 10 to 25µm with aspect ratios of 5:1. With a lower aspect ratio, the difficultly on via creation and process complexity is reduced.

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Anyhow, the vias must be void free to offer a high reliability and low resistance contact. Thus, a variety of structures and processes have been demonstrated using copper, tungsten, and other materials. Each process flow in the fabrication of TSVs has its own challenges, and the structure as well as the choice of materials for filling the via depend on the specific application of the 3D integration (C. S. Patel et al, 2005). By looking at the Sparameter result, (F. Liu et al, 2010) shows the S11 and S21 are -21.78dB and -0.94dB respectively at 25GHz operating frequency. At 45GHz, the de-embedded result for S11 is -17.36dB and S21 is -1.15dB.