Q1. Explain layout design rule.
Ans: A set of geometric constraints or rules which are used to manufactured the physical mask layout of any circuit, these are generally called layout design rules. The main objective of design rules is to achieve, a particular process, which maintains a high overall yield and reliability while using the smallest possible silicon area.
Design rules can be used in two ways
(i) Micron rules, in whi ch the layout constraints such as minimum feature sizes and minimum allowable feature
separations are stated in terms of absolute dimensions in micrometers, or,
(ii) Lambda rules, which specify the layout constraints in terms of a single parameter ( ) and thus allow linear, proportional scaling of all geometrical constraints.
Rule number Description λ-Rule
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R17 Minimum active contact to active edge spacing 1λ R18 Minimum active contact to metal edge spacing 1λ R19 Minimum active contact to poly edge spacing 3λ R20 Minimum active contact spacing 6λ (on different active regions)
Fig 4.1 shown the layout of a particular circuit with rule number, which intimates the dimension of each diffused material in the circuit components in lambda.
Fig 4.1 Illustration of layout design rule for circuit
Q 2 Explain the design rule for any circuit layout taking an example of CMOS invertor.
Ans As it is known that the CMOS inverter circuit consists of PMOS and NMOS transistors.
Each transistor is created according to the design rule. In designing our main goal is to create minimum size transistor. Using minimum diffusion contact size the width of the active area is then determined and the minimum separation from diffusion contact to both active area edges. The width of the poly-silicon line is typically taken as the minimum poly width as shown in fig 4.2 .
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Fig.4.2 Design rule constraints which determine the dimensions of a minimum-size transistor Then, the overall length of the active area can be determined using this formula
L= minimum poly width + 2 x minimum poly-to - contact spacing + 2 x minimum spacing from contact to active area edge.
The PMOS transistor is placed in an n-well region. The minimum separation between the n+ active area and the n-well, distance between the NMOS and the PMOS transistor can be determined. The poly-silicon gates of the NMOS and the PMOS transistors are usually aligned as shown in fig .
During finalization metal connections are made for input, output, ground and VDD. Finally the complete layout of CMOS inverter is obtained as shown in fig 4.3 (a) and 4.3 (b)
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Fig 4.3(a) Placement of one NMOS and one PMOS transistor, and (b) Complete mask layout of the
CMOS inverter
Q 3 Design a layout for NAND and NOR gate.
Ans Here we consider a two inputs NAND gate. While designing layout 4 transistors are required. Firstly we design a CMOS NAND logic circuit then using lambda design rule we create layout of NAND gate as shown in fig4.4 .
In this circuit layout colors are assigned to the layers as written below Colors of layers
polysilicon (gates) : Red Doped n+/p+ (active) : Green N-Well : Yellow Metal 1: BLUE Metal 2 : Grey Contacts: Black X‟s
Using these colored layers layout of NAND gate is made followed by CMOS NAND logic circuit.
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Fig 4.4 NAND layout
Similarly for NOR gate firstly CMOS logic circuit is designed using this circuit NOR layout is created as shown in fig 4.5.
Fig 4.5 NOR layout
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Q 4 What is Eular rule and design a stick layout for given function using Eular rule:
F =
Ans To determine common path in CMOS logic circuit Euler Graph Technique can be used.
Using this path easily layout can be designed with minimum connection among all the circuit elememts. Start with either NMOS or PMOS tree and circuit components are replaced by connecting lines like transistor segments, labeling devices, and circuit nodes.
By using the Euler path technique polysilicon lines are rearranged to get optimum layout.
• Find a Euler path in both the pull-down tree graph and the pull-up tree graph with identical ordering of the inputs.
Fig 4.6 (a) CMOS circuit (b) Euler path of NMOS and CMOS circuit
Fig 4.7 Stick layout diagram
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As shown in fig 4.7, a stick layout is made by using the order of NMOS and PMOS inputs which are common for both and reduce the size and complexity of the conventional layout.
Q 5 Draw the layout of following equation:
Ans As shown in fig 4.8 firstly CMOS circuit is designed and then euler path is created to obtain a common path to reduce the size of the layout.
Fig 4.8 (a) CMOS logic circuit (b) Euler path for NMOS and PMOS circuit
Fig 4.9 Circuit layout of equation
Fig 4.9 shows the circuit layout of given equation , it is created by using circuit layout lambda rules.
For free study notes log on: www.gurukpo.com Q6 Explain the layout optimization and performance.
Ans : There are basic three components which are used to built layout: transistors, wires and vias. Integrated chip designing the design rules determine the low level properties:
How we can design small logic gates
To reduce the delay, small joining wires connecting gates can be made.
Some fabrication errors are also introduced, which should be minimized as:
1. A wire or other feature made too wide or too narrow, can create fabrication problem and reasons may be;
(i) Error due to photolithographic (ii) Local materials
2. Planarization problem:
(i) Due to deposition of metal wire in oxide area
(ii) This over metal area is smoothened by chemical methods and due to this process sometime lead breaks in layers.
3. If wider wires are used, then it may get shorted and narrow wires may burn out, so no current at all.
(i) Due to minimum width rules give a minimum size (ii) Minimum distance between layout components.
For the optimum layout design, designer should design the components in lambda, the size of the smallest feature in a layout. By choosing value for lambda, set the dimension of layout. Layout editor, Design rule checkers (DRC), Circuit extractors are layout design and analysis tools, which are used to design and simulate the CMOS circuits.
VLSI 35 developed in 1980s. VHDL can be defined as follows
It is a programming language that is designed and optimized for digital circuit design and modeling. This language is used to describe the physical, structural and behavioral characteristics of digital systems at multiple level of abstraction.
The language that allows to validating the design of a device prior to fabrication.
Language which provides a range of features, that support the simulation of digital circuits.
VHDL allows you to specify:
The components of a circuit.
Their interconnection.
The behavior of the components in terms of their input and output signals.
Features of VHDL Model:
Sub-components and their interconnections are described in the design as components.
It contains dataflow description of circuit and concurrent statements execute when data is available on their inputs.
Functional and possibly timing characteristic are described in behavioral description using VHDL concurrent statements and processes. The process execute sequentially until it gets suspended by a wait statement.
Packages is the combination of common declaration, constants, and/or subprograms to entities and architectures.
Generics is used to communicate information from the external environment to the designer.