In the early days of programming, data structures were often the result of a curious blend of trying to come up with a data format that best suited the programmer and what best suited the current hardware. One of the more
enduring structures that came from this time is the ‘‘binary coded decimal’’ (most often referred to by its acronym ‘‘BCD’’) which used four bits, like hexadecimal values, but only allowed the values of zero through nine rather than the full 16 values that were possible (as shown in Table 4-5). The reason for using this data structure has largely disappeared in computer systems, but it is still a viable and useful method of handling data in digital electronics and one that you should keep in your ‘‘hip pocket’’ when you design circuits.
The original reason for using the BCD data format in computer programming was its elimination of the need to add code to the program to convert a binary or hex number into decimal. The code storage required for the conversion was expensive and the processors were nowhere near as possible as what is available today. Using decimal values was actually an optimal way of processing data in these old systems.
The lasting legacy of this is the number of standard chips that can process BCD values just as easily as other standard chips can process hexadecimal values and will allow you to design circuitry that works with decimal values just as easily as if you were working with hex values.
While this is getting a bit ahead of things, I want to give the example of designing a delay that holds back a signal for 100 seconds. Using traditional binary logic, which only works with bits that are a power of two, you would have to design a circuit that compares a counter value and indicates when the
Table 4-5 Decimal digits with binary and BCD decimal equivalents.
Decimal Binary BCD Decimal Binary BCD
0 B’0000’ 0 8 B’1000’ 8 1 B’0001’ 1 9 B’1001’ 9 2 B’0010’ 2 10 B’1010’ Invalid 3 B’0011’ 3 11 B’1011’ Invalid 4 B’0100’ 4 12 B’1100’ Invalid 5 B’0101’ 5 13 B’1101’ Invalid 6 B’0110’ 6 14 B’1110’ Invalid 7 B’0111’ 7 15 B’1111’ Invalid
value ‘‘100’’ was reached and reset itself. When using digital electronic chips that are designed for BCD values, the comparator function is not required, as each BCD digit cannot be greater than ‘‘9’’ and, cascaded together, they can only count to a maximum value of ‘‘99’’ to ‘‘00’’.
This may seem like a trivial example, but you will find a number of cases like this one where you will have to create circuits that work on base 10 data and by using chips which are designed for BCD values, the complexity of your work will be greatly reduced.
Going back to Table 4-5, the production of the ‘‘invalid’’ indication is worthy of some discussion as it provides a good example of how gate optimization is not always as straightforward as you might expect.
In most BCD chips, if the value of 10 or more is passed in the binary bits, then the value is converted to zero and a carry indication is output. Using the tools presented in Chapter 2, you should be able to derive the sum of products formula for the positive active ‘‘invalid’’ indicator as:
Invalid¼ ðA3A2Þ þ ðA3A2Þ
and using the conversion formulas of Chapter 2, you would simplify the ‘‘invalid’’ formula above to:
Invalid¼A3 ðA2þA1Þ
Figure 4-1 shows the AND/OR gates for this function along with the ‘‘NAND equivalent’’ function beneath it. The NAND equivalent was chosen by assuming that the function would be implemented in TTL. While this circuit looks a bit complex, if you follow it through, you will find that it provides the same function as the AND/OR combination above it.
It will probably surprise you to find out that this circuit is not optimal by any measurement: you can do better in terms of the number of gates, the time
it takes a signal to pass through the gates and in providing a constantly timed output. The circuit at the bottom half of Fig. 4-1 will respond in two gate delays if A3 changes and in four gate delays if A2 changes. For many circuits, this is not a problem, but when you are working with high-performance designs, a variable output delay can result in the application not working correctly and being almost impossible to debug.
A much better approach to optimizing the circuit is to work at converting it to the basic gate used by the technology that you are working with and then optimizing this. Going back to the original ‘‘Invalid’’ equation:
Invalid¼ ðA3A2Þ þ ðA3A2Þ
I can convert the OR to a NAND, by inverting its two parameters (according to De Morgan’s theorem), ending up with:
Invalid¼!ð!ðA3A2Þ !ðA3A2ÞÞ
It is probably astounding to see that the function provided by the mess of NAND gates in Fig. 4-1 can be reduced to the three simple gates required by the formula above. Along with reducing the number of gates, you should also notice that the maximum number of gate delays is two, regardless of which bit changes.
Looking at the NAND circuits in both diagrams, you are probably at a loss as to how you could reduce the NAND circuit in Fig. 4-1 to the three
gates of the optimized circuit. Personally, I would be surprised if you could; when I look at the two circuits, they look like they provide completely different functions.
What I want to leave you with is an example of how looking at a logic function from different perspectives can result in radically different circuits with surprisingly different parameters. In the first case, I reduced three gates to two, to end up with six NAND gates, while in the second, I avoided reducing the basic function and converted it directly to a much more efficient three NAND gate circuit.
In going through this exercise to produce the ‘‘invalid’’ output for BCD, I hope that you can apply this knowledge for creating circuits that work with different base systems than just a power of two. In some cases, you may have to work with numbers that are base 9 or 13 and using the example here, you should have some idea of how to keep the values within certain ‘‘bounds’’.