3.2 BitMan
3.2.1 Bitstream Format
A bitstream is a sequence of commands, which can be split into three logical parts: a header, a body and a footer. The header and footer are a set of mandatory commands, while the body contains the configuration data for the frames.
Frames
Frames are blocks of configuration data. A frame represents the smallest amount of configuration data that can be written. Although, since Xilinx guarantees glitchfree operation if the same value is written to a configuration bit, single bit granularity updates are possible. Each frame contains a family specific number of 32-bit words. Depending on the resource to be configured multiple frames might be necessary to reconfigure the resource.
To understand the layout of the frames, consider the address format in Fi- gure 3.1. The address contains five parts: 1) block type, 2) topbit, 3) row,
4) column, and 5) minor. Seven-series Field Programmable Gate Arrays (FPGAs) are split into a top and bottom half, each containing half of the rows, thus the top bit can be regarded as an extension to the row. Row, column, and top bit are 2d coordinates on the device. By looking at the appropriate point on the device, it is possible to identify what kind of resource the frame configures. Furthermore, the frames are grouped into block types by the functional unit they configure: Configurable Logic Blocks (CLBs), I/O and CLK are block type 000, whileBRAM contents are block type 001. While block types 010 and 011 are mentioned in the documentation, and block type 100 has been spotted in bitstreams its precise definition remains unclear. As mentioned before, several frames worth of configu- ration data might be required for a resource type. These frames are enumerated and addressed by the minor address bits group.
The address format is family specific as shown in Figure 3.1, the number of bits for the different parts varies and the top bit has only been introduced with the 7 Series family.
42 CHAPTER 3. PARTIAL RECONFIGURATION 31 23 15 7 0 Minor T Row Column Block Type 25 2221 16 6 7 Series 31 23 15 7 0 Minor Row Column Block Type 25 22 16 UltraScale UltraScale+ 6 31 23 15 7 0 Minor Row Column Block Type 26 23 17 7 Reserved Reserved Reserved
Figure 3.1: Frame address formats for various device families. From top to bottom: 7 Series, UltraScale, and UltraScale+.
frame writes are possible writing multiple frames in one operaton. In the case of a multi-frame write, the internal configuration access port (ICAP) module increments the frame address. TheICAP module is aware of the maximum values of the address bits, and wraps the counters accordingly. This includes the minor address, which depends on the resource type, and thus on the current row, column, and top bit. Figure 3.2 illustrates the implicit frame layout. Frames are first divided by their block type. Then they are arranged in the clock region rows, to which the top bit (not in the figure) is a prefix, and the tile columns. Each of these columns is described by a number of frames depending on the column type. The frames describing a column are indexed by the minor address and lastly the word indices.
Header
The header contains the initialisation data for the ICAP. It starts with a synchro- nization and automatic detection of the bus width, and an identifier for the device the bit stream targeted. Furthermore, a watchdog timer and an (optionally) CRC check are set up. While ICAPwill refuse reconfiguration if the device ID in the bitstream does not match the device,BitMancan change device IDs. This allows for reconfiguration if the family (and thus the configuration data format), is the same. The header also sets general options, like decryption of the bitstream, and clock frequency.
3.2. BITMAN 43 R ow 1 R ow 0 R ow 2 BRAM CLB DSP I/O GTH
X0Y2
X1Y2
X0Y2
X1Y2
X0Y2
X1Y2
clock r
egion
01 2 0 1 Column Blocktype 000 Blocktype 001 CLKROW ... ... 0 1 2 n Minors W or d Indices44 CHAPTER 3. PARTIAL RECONFIGURATION
Body
The body contains the configuration frames of the bitstream. For full bitstreams, that configure the entire device, this is usually a single frame write command. Par- tial bitstreams, on the other hand, usually contain several frame write commands, as a rectangular region on the device maps to separated chunks in the serialized bitstream. If bitstream compression is enabled the frames are grouped by their content. All frames with the same content are written using multi-frame-write commands. Multi-frame-writes require the configuration data once and duplicate it to several addresses, thus saving space.
Footer
The footer of a bitstream controls the startup sequence. The startup sequence contains several optional steps, for example activating I/O’s, enabling sequential elements like flip-flops, or waiting formixed mode clock manager (MMCM)startup. The footer closes with a sequence of NOOPs, ensuring that the frames have actually been written at the destination, before completing reconfiguration by issuing a DESYNC command.
Further information on the bitstream format and partial reconfiguration can be found in [11, 19]. Appendix B shows an excerpt from a bitstream, as seen by BitManin particular the header and footer.