The I/O Board

The IOB has a spatial dimension of approx. 229.3 mm × 22.6 mm, which is identical to that of a PRB. A sketch of the IOB prototype that has been developed within the scope of this thesis is illustrated in figure 5.8. In the following, revision-specific details are distinguished by using the

(a)Top view

(b)Bottom view

Figure 5.8:Sketch of the IOB layout.

term IOB-rev0.1 for the prototype version, while IOB-rev1.0 refers to the revised version of the board that will most likely be applied in the final DSSC. If no specific details need to be stressed, IOB is used as a general term.

The central element of the IOB-rev0.1 is a Xilinx Spartan-6 XC6SLX45T-3-CSG324-C FPGA. The main reasons for choosing this device are the number of featured high-speed transceivers and the physical size of the chip. An LX45T offers four GTPs at 3.125 Gb/s each, which is sufficient for the expected data rate of approx. 4.21 Gb/s of a sensor module. The CSG324 package with 15 mm × 15 mm is the smallest size available for an LX45T and allows a dense implementation on the PCB. For the prototype, a device that features commercial temperature range (0◦_{C to +85}◦_C) is used due to the fact that the initial test system will be operated at room temperature only. Moreover, the difference in electrical characteristics between commercial and industrial (−40◦_{C to} +100◦_{C) temperature range is negligible according to the Spartan-6 data sheet [45]. Speed grade -3} has a few advantages over -2, mainly related to the minimum and maximum ratings of the FPGA clock management specifications. A speed grade of -1 drops out, since there is no LXT device available in this category. Since the DSSC system will be cooled down to approx. −20◦_{C, the} IOB-rev1.0 will be supplied with an XC6SLX45T device of speed grade -3 featuring an industrial temperature range.

Figure 5.9 illustrates the connectivity of the IOB FPGA. A 60-pin terminal strip of type TOLC (115-02-L-Q-A) and a 60-pin socket strip of type SOLC (115-02-L-Q-A) (both from Samtec) connect the IOB to the MIB and the Main Board, respectively. Contrary to the PPT, the IOB has no flash storage for the firmware. Instead, the FPGA fabric is configured via a JTAG interface hosted by the PPT. A slow-control interface provides the inter-communication between the PPT and the IOB, which is used to send commands for remotely control the IOB and its peripheral electronics. Two different sets of control signals from the IOB FPGA are provided to the PRBs using octal signal drivers of type TI CD74HC541PW and Fairchild 74AC541MTC, respectively. The first device operates the shift registers that define the status of the ASIC power nets. The latter one controls gate drivers that generate the clear pulses for the DEPFET sensor.

The 1-to-8 fanout clock buffers (National Semiconductor LMK01010) residing on the Main Board directly connect to the IOB FPGA via a serial interface. The interface provides access to internal

5.2 Hardware Implementation

Figure 5.9:Connectivity of the IOB FPGA.

configuration registers, which for example allow adjusting the input-to-output delay of the clock signal. This feature is essential to compensate for signal skew, as the clock signals distributed by the LMK devices must have a well-defined phase relation to the electron bunch timing.

The clock signals used as ADC sampling clock and for ASIC fast-control are received two ultra- precision fanout clock buffers from Micrel. An SY89200U (1-to-8) and an SY89832U (1-to-4) each duplicates one of the input clocks ADCCLK and XCLK and distributes a copy to the clock buffers of the two Main Board sections. A third copy of each clock signal is provided to the IOB FPGA for purposes of synchronizing and data recording. As the Spartan-6 specification permits a maximum clock input frequency of 400 MHz only, the frequency of ADCCLK signal is divided by two8 _before feeding into the Spartan-6. Since the ASICs send the pixel data synchronously to half the frequency of ADCCLK, there is no downside of doing so.

The ASIC data are received over signal lines that directly link the SOLC to an FPGA I/O bank. After de-serializing inside the FPGA, data are forwarded to the PPT via the four (three9_{) GTP} lanes and the TOLC.

The power for the sensors is received over the TOLC and supplied via the SOLC. For reasons of minimizing the power consumption during the readout phase, the power is gated by connecting the corresponding nets to a set of FETs. The IOB FPGA operates the FETs by means of LM5112MY FET drivers from National Semiconductor.

An XO of type SiLabs SI530FA156M25DG generates the local clock for the FPGA. The clock signal is duplicated by a Micrel SY58608U 1-to-2 fanout buffer, which provides the copies to the FPGA as fabric clock and separate reference clock for the high-speed transceivers.

As for the local power required by the IOB electronics, a set of DC/DC switching converters derive additional supply voltages from the 3.3 V main power net supplied over the TOLC. Two TI TPS62510 devices produce separate 1.2 V power networks, which are used as FPGA core / I/O supply voltage and for powering the GTP high-speed transceivers. A single TI TPS54319 device generates the 2.5 V supply voltage for another FPGA I/O bank and various peripheral electronic components.

8_{In the final system it might also be divided by four and multiplied accordingly inside the FPGA fabric} 9_{Latest PPT concept foresees only three links.}

The DSSC Front-end DAQ