Number of analog input channels = 2–16 single ended or 1–8 differential Analog input ranges = ±5; 0–10; ±10; 0–24 V
Buffer Size: 512–2048 samples
Input gain ranges (programmable) = 1, 2, 5, 10, 20, 50, 100
Sampling rate for A/D conversion = 10 k samples/s (100 kHz) to 1 MS/s Word size (resolution) of ADC = 12 bits, 16 bits
Number of D/A output channels: 1–4 Word size (resolution) of DAC = 12 bits
Ranges of analog output = 0–10 V (unipolar mode); ±10 V (bipolar mode) Number of digital input lines = 12
Low voltage of input logic = 0.8 V (maximum) High voltage of input logic = 2.0 V (minimum) Number of digital output lines = 12
Low voltage of output logic = 0.45 V (maximum) High voltage of output logic = 2.4 V (minimum) Number of counters/timers = 3
Resolution of a counter/timer = 16 bits Input impedance: 2.4 kΩ at 0.5 W Output impedance: 75 Ω
binary 1. The combination of these bits, which form the digital word in the DAC register, will correspond to a numerical value of the analog output signal. Then, the purpose of the DAC is to generate an output voltage (signal level) that has this numerical value and maintain the value until the next digital word in the arriving digital data sequence is converted into the analog form. Since a voltage output cannot be arbitrarily large or small for practical reasons, some form of scaling would have to be done in the DAC process. This scale will depend on the reference voltage vref used in the particular DAC circuit.
A typical DAC unit is an active circuit in the form of an IC chip. It may consist of a data register (digi-tal circuits), solid-state switching elements, resistors, and op-amps powered by an external power supply (possibly that of the host computer), which can provide the reference voltage for the DAC. The reference voltage will determine the maximum value of the DAC output (full-scale voltage). As noted before, the IC chip that represents the DAC is usually one of the many components mounted on a printed circuit (PC) board, which is the DAQ card (or I/O card or interface board or DAQ and control board). This card is plugged into a slot of the host personal computer or PC (see Figures 2.34 and 2.35).
2.7.1.1 DAC Operation
The typical operation of the DAC chip is based on turning on and off of semiconductor switches (e.g., CMOS switches) at proper times, as governed by some logic dependent on the digital data value. This switching will determine the output of an op-amp circuit, which is the analog output of the DAC. There are many types and forms of DAC circuits. The form will depend mainly on the DAC method, manufac-turer and requirements of the user or of the particular application. Most types of DAC are variations of two basic types: the weighted type (or summer type or adder type) and the ladder type. The latter type of DAC is more desirable and more power efficient even though the former type could be somewhat sim-pler and less expensive. Another straightforward and simsim-pler (but possibly less accurate) method uses a PWM chip. Two representative DAC methods are outlined next.
2.7.1.1.1 Ladder (or R–2R) DAC
A DAC that uses an R–2R ladder circuit is known as a ladder DAC or R–2R DAC. This circuit uses only two types of resistors, one with resistance R and the other with 2R. Hence, the precision of the resistors is not as stringent as what is needed for the weighted-resistor DAC. Schematic representation of an R–2R ladder DAC is shown in Figure 2.36. Switching of each element occurs depending on the corresponding bit value (0 or 10) of the digital word. The sum of the corresponding voltage values is generated by the op-amp, which is the analog output.
To obtain the I/O equation for the ladder DAC, suppose that the voltage output from the solid-state switch associated with the bit bi of the digital word is vi. Furthermore, suppose that vi is the voltage at node i of the ladder circuit, as shown in Figure 2.36. Now, writing the current summation at node i we get
v v
Equation 2.81 is valid for all nodes, except for nodes 0 and n − 1. It is seen that the current summation for node 0 gives
The current summation for node n − 1 gives
v v
Now, since the positive lead of the op-amp is grounded, we have vn -1=0. Hence,
1
2vn-1= -v n-2-v (2.83)
Next, by using Equations 2.81 through 2.83, along with the fact that vn -1=0, we can write the following series of equations:
FIGURE 2.36 The circuit of ladder DAC.
If we sum these n equations, first denoting
Hence, the analog output is proportional to the value D of the digital word and, furthermore, the full-scale value (FSV) of the ladder DAC is given by
FSV =æ
-èç ö
ø÷
1 1
2n vref (2.86)
Note: The same results are obtained for a weighted-resistor (adder) DAC.
2.7.1.1.2 PWM DAC
As noted before, in PWM, the pulse width is varied (modulated) in pulse sequence of fixed amplitude.
Consider the pulse signal shown in Figure 2.37a, where T is the pulse period and p is the fraction of the period in which the pulse is on.
When expressed as a percentage (i.e., 100p), p represents the duty cycle of the pulse. Hence, the two extremes of the modulation are, duty cycle of 0% where the pulse is fully off and 100% where the pulse is fully on during the entire period. Also, it is clear that the average value (i.e., the dc value) of the pulse
(b)
FIGURE 2.37 (a) Duty cycle of a PWM signal and (b) operation of a PWM DAC.
is pvref. It follows that when the duty cycle varies from 0% to 100%, the dc value of the pulse signal var-ies in proportion, from 0 to vref. This principle is used in a DAC that uses a PWM chip. Specifically, the PWM signal is generated by switching the PWM on for a time period that is proportional to the value of the digital word. The resulting signal is low-pass filtered with a very low frequency cutoff, as shown in Figure 2.37b. The magnitude of the resulting analog signal is almost equal to the dc value of the PWM, which is pvref. In this manner, an analog output in the range 0 to vref is obtained, in proportion to the value of the digital word in the DAC register.
2.7.1.1.3 DAC Error Sources
For a given digital word, the analog output voltage from a DAC would not be exactly equal to what is given by the analytical formulas (e.g., Equation 2.85). The difference between the actual output and the ideal output is the error. The DAC error could be normalized with respect to the FSV.
There are many causes of DAC error. Typical error sources include parametric uncertainties and variations, circuit time constants, switching errors, and variations and noise in the reference voltage.
Several types of error sources and representations of a DAC are given in the following.
1. Code ambiguity: In many digital codes (e.g., in the straight binary code), incrementing a number by a least significant bit (LSB) will involve more than 1 bit-switching. If the speed of switching from 0 to 1 is different from that for 1 to 0, and if switching pulses are not applied to the switching circuit simultaneously, the switching of the bits will not take place simultaneously. For example, in a 4-bit DAC, incrementing from decimal 2 to decimal 4 will involve changing the digital word from 0011 to 0100. This requires 2-bit switchings from 1 to 0 and 1-bit switching from 0 to 1. If 1 to 0 switching is faster than the 0 to 1 switching, then an intermediate value given by 0000 (deci-mal zero) will be generated, with a corresponding analog output. Hence, there will be a momen-tary code ambiguity and associated error in the DAC signal. This problem can be reduced (and eliminated in the case of single-bit increments) if a gray code is used to represent the digital data.
Improving the switching circuitry will also help reduce this error.
2. Settling time: The circuit hardware in a DAC unit will have some dynamics, with associated time constants and perhaps oscillations (underdamped response). Hence, the output voltage cannot instantaneously settle to its ideal value upon switching. The time required for the analog output to settle within a certain band (say ±2% of the final value or ±1/2 resolution), following the appli-cation of the digital data, is termed settling time. Naturally, settling time should be smaller for better (faster and more accurate) performance. As a rule of the thumb, the settling time should be less than half the data arrival period. Note: Data arrival time = time interval between the arrival of two successive data values = inverse of the data arrival rate.
3. Glitches: Switching of a circuit will involve sudden changes in magnetic flux due to current changes. This will induce voltages, which will produce unwanted signal components. In a DAC circuit, these induced voltages due to rapid switching can cause signal spikes, which will appear at the output. At low conversion rates, the error due to these noise signals is not significant.
4. Parametric errors: The resistor elements in a DAC may not be very precise, particularly when resis-tors within a wide range of magnitudes are employed, as in the case of weighted-resistor DAC.
These errors appear at the analog output. Furthermore, aging and environmental changes (primar-ily, change in temperature) will change the values of circuit parameters, resistance in particular.
This will also result in DAC error. These types of error due to imprecision of circuit parameters and variations of parameter values are termed parametric errors. Effects of such errors can be reduced by several ways including the use of compensation hardware (and perhaps software), and directly by using precise and robust circuit components and employing good manufacturing practices.
5. Reference voltage variations: Since the analog output of a DAC is proportional to the reference voltage vref, any variations in the voltage supply will directly appear as an error. This problem can be overcome by using stabilized voltage sources with sufficiently low output impedance.
6. Monotonicity: Clearly, the output of a DAC should change by its resolution (Δy = vref/2n) for each step of one LSB increment in the digital value. This ideal behavior might not exist in some prac-tical DACs due to such errors as those mentioned earlier. At least the analog output should not decrease as the value of the digital input increases. This is known as the monotonicity require-ment, and it should be met by a practical DAC.
7. Nonlinearity: Suppose that the digital input to a DAC is varied from (0 0…0) to (1 1…1) in steps of one LSB. Ideally, the analog output should increase in constant jumps of Δy = vref/2n, giving a staircase-shaped analog output. If we draw the best linear fit for this ideally monotonic staircase response, it will have a slope equal to the resolution/bit. This slope is known as the ideal scale fac-tor. Nonlinearity of a DAC is measured by the largest deviation of the DAC output from this best linear fit. Note: In the ideal case, the nonlinearity is limited to half the resolution (1/2Δy).
One cause of nonlinearity is faulty bit transitions. Another cause is circuit nonlinearity in the conven-tional sense. Specifically, due to nonlinearities in circuit elements such as op-amps and resistors, the analog output will not be proportional to the value of the digital word as dictated by the bit switchings (faulty or not). This latter type of nonlinearity can be accounted for by using calibration.
Multiple DACs in a single package are commercially available; for example, a package of 16 DACs each of 16-bit resolution and independently software-programmable or pin-configurable in the output voltage range ± 10 V; with internal 16:1 analog MUX. Typical ratings of a commercial DAC chip are given in Box 2.4.
2.7.2 Analog-to-Digital Converter
The measured variables of an engineering system are typically continuous in time; they are analog sig-nals. Furthermore, common applications that use these signals, such as performance monitoring, fault diagnosis, and control, will require digital processing of these signals. Hence, the analog signals have to be sampled at discrete time points, and the sample values have to be represented in the digital form (according to a suitable code) to be read into a digital system such as a computer or a microcontroller.