Case Study – Main Outcomes

This work reported in this submission two and described in this chapter developed the

preliminary design to cost process. This can be summarised as a process for

comparing a hardwired original electrical architecture with a LIN based alternative

and ascertaining a cost target for adding LIN communications capability to electrical

architecture nodes. Key steps were:

1. develop an appropriate wire model for the wire type (intra- and inter-zone in this

case)

2. ascertain the number of wires and types that are to be added or removed (i.e. by

signal substitution analysis)

3. analyse the sensitivity for estimating the target add-on nodal cost to be achieved

for the LIN candidate to be the same price or lower than the hardwired original

The methodology of the analysis presented focused on a comparison of the

costs of the bill of materials of two different methods of electrical system integration,

in this case hardwired and LIN based architectures. It is important to note that it was

not a methodology for cost estimation but a methodology for comparing two

architectures. Cost estimation itself would require the designers to go a lot further

of the research presented was to establish a methodology with which candidate

electrical architectures can be realistically compared on a cost basis at a very early

stage of design. Wire cost was investigated and this led to the identification of a

target LIN node cost that should be met to help ensure that the LIN architecture will

be of lower cost than the hardwired alternative. Historical wire cost data was studied

but there was no data available on the LIN nodal costing or some of the other costs

that might affect the choice of architecture. Therefore a number of areas of further

work were recommended.

The architecture cost comparison methodology presented did not take account

of other costs such as non-recoverable software development costs associated with

LIN, cross platform portability (which would amortise the costs across a number of

platforms), vehicle assembly, warranty, weight savings (which will ultimately reduce

costs for both the customer in terms of fuel consumption and the manufacturer in

terms of CO2 based taxation). Making a justification for the use of LIN over a

hardwired architecture, based on the cost of bill of materials alone, appeared to be

very challenging and as it resulted in very low target nodal costs. Therefore there is

motivation for research into the effects of other factors on both LIN and hardwired

architectures.

Use of Process

A key point about the use of the process developed is it cannot be used to predict the

cost of an alternative architecture based on a particular harness. However it does

have two other applications; estimation of target nodal cost or estimation of

If the target nodal cost for adding LIN communications (CNode) is not known,

the process can be used to estimate the target CNode that must be met for the LIN

candidate architecture to be the same cost as the hardwired original. This was the

process followed for the mass vehicle wiring harness manufacturer case study that

was described in submission two.

It can also be used to estimate whether a move from hardwired integration to

LIN would result in a cost reduction or increase. This is the case if CNode is known,

e.g. if legacy ECUs are already available and are to be used in a new architecture

design. Use of the wire model information and CNode values will give delta values

from the architecture equations.

It was recommended that further work should include an investigation of how

target nodal cost can be achieved and how it varies with changes in architecture and

signal requirements. The aim of this recommendation was to help ascertain whether

the target nodal cost values obtained within this submission are realistic and

achievable (e.g. 1.61 to 1.9 Euros). It was stated that it would be interesting to

understand the cost of FETs, relays, switches and the size of application software and

how this affects the target cost of a network node. This recommendation gave

motivation to the work in submissions three and four since they helped uncover some

of the cost implications of LIN communications and embedded software generally.

Submission three investigated the relationship between microcontroller ROM

and RAM capability and microcontroller unit cost. Data from the semiconductor

manufacturer Microchip for their PIC16 and PIC18 microcontroller families was

investigated. It was found that there was a relationship between cost and ROM/RAM

capability with the implication being that an increase in the LIN communications

software ROM and RAM requirements. Therefore an increase in the LIN

communications embedded software ROM and RAM requirements would result in

increased microcontroller cost. One other output from submission three was that it

was discovered that there tends to be a linear relationship between the ROM and

RAM capability across a microcontroller family. This therefore provided the basis of

a microcontroller capability assessment process for assessing how well it is suited for

a particular piece of embedded software (e.g. in this case a LIN communications

stack). This is described further in chapter 5.

The relationship between LIN communications requirements and LIN

communications software stack ROM/RAM requirements, was explored further in

submission four. It was found that it was possible to estimate ROM/RAM

requirements of the LIN communications stack from information such as number of

nodes, signals, messages etc. using regression models. The process for this is

described in chapter 5.