Chapter 5 Conclusions

[80]. The characteristics for the cases with the quiescent point set to the origin and with the quiescent point set to the class B operating point consolidate in the trapping zone of the I-V plot showing that the trapping process is completed in a very short time (τdl

trap ≪ pulse width). For the devices investigated in this work, this is also observed for

the measurements with illumination (see figure 5.37). In this case, the consolidation of currents in the trapping zone is shown obviously.

5.5. Chapter 5 Conclusions

Pulsed I-V and pulsed time domain measurements for characterization of trapping effects have been discussed in this chapter. The pulsed I-V characteristics measured with differ- ent quiescent points show different drain currents since the states of the trapped charges are different. The requirements of the measurements for trapping characterization are:

ˆ Thermal effects should be excluded from the measurement results so that only the

trap-related effects are present.

ˆ Effects related to alteration of gate- and drain voltages should be measured sepa-

rately.

ˆ Dependency of trapping effects on the channel temperature, the device gate width

and bias voltages should be determined.

For the extraction of time constants, measurements in time domain were performed. Since the devices investigated in this work have shown both gate lag and drain lag effects, current lag measurements by pulsing the voltages along the hyperbola of a constant power are not appropriate since the gate- and drain voltages are changed simultaneously during the measurements. To separate the gate- and drain lag effects, standard gate- and drain lag measurements have been performed for the extraction of time constants. The current was kept low during the pulse to minimize the influence of self-heating on the result [71]. Devices with different gate width have been measured at different temperatures to inves- tigate dependency of those parameters on time constants. In order to separate current lag caused by the alteration of gate- and drain voltages, the measurements had been performed with a constant drain voltage and a pulsed gate voltage for gate lag and vice versa for drain lag. Since heat and illumination can provide energy that contributes to the emission of charge carriers from traps, the time constants decrease with increasing temperature or direct illumination on the device. From the measurement results, de- pendency on the gate-width is not well-defined for the devices investigated in this work. Assuming that the current lags due to traps can be described by an RC-circuit, R is reversely proportional whereas C is directly proportional to the area. Thus the change of device gate width leads only to an insignificant change of the time constants.

Drain lag is reported in the literature as a buffer trap-related effect whereas, both surface and buffer traps are involved in case of gate lag. The current degradation in I-V charac- teristics have shown a bias-dependency in case of buffer trap-related gate lag whereas the

88 Chapter 5. Characterization of Memory Effects due to Trapping

bias-dependency is not present in case of the surface trap-related gate lag. The existence of buffer traps can also be recognized by plotting the current over the initial gate voltage of the pulse. In case buffer traps are involved in gate lag, the transconductance value increases as Vgsq falls below the cut-off threshold voltage VTO.

Time domain measurements have been performed for the extraction of the trapping time constants, whereas current collapse measurements have been performed to determine the current deviation due to charge carrier traps in the entire I-V characteristic. Standard current collapse measurements compare the maximum current available from the device measured with the quiescent point Vgsq = Vdsq= 0 with the case where the quiescent

point is set to the class B or class C operating point (Vgsq ≤ VTO, Vdsq= 0) and the

current is reduced due to trapping effects. However, for modeling purpose, it is advan- tageous to investigate current collapse due to changes of the gate- and drain quiescent voltages separately. To achieve this, the I-V characteristics have been measured for different Vgsqwhile Vdsq was constant and vice versa.

In order to assure constant thermal conditions during the measurements, the quiescent points of the current collapse measurements were chosen in a way, that no static current flows. Beside the current degradation, a shift of the knee voltage was observed in case of a drain lag-related current collapse. Compared to the case with Vdsq = 0, the current

degradation in case of a high Vdsqis significant if Vds < Vdsq and marginal if Vds > Vdsq.

This effect is a consequence of the asymmetry in trapping/detrapping processes of drain lag with different trapping and detrapping time constants.

Charge carrier traps in different locations of the investigated devices lead to various effects. These effects are categorized according to the locations of the traps.

Buffer Traps

ˆ Gate lag with time constant in ms regime ˆ “Valley” in the 3D gm plot

ˆ In the plot Ids over Vgsq, the reduction of Ids increases after Vgsq falls below VTO. ˆ Considerable dependency on temperature and illumination

ˆ Drain lag

ˆ Current collapse (Ids-degradation in case of a high Vdsq compared to the case of

Vdsq = 0)

Surface Traps

ˆ Gate lag with time constant in µs regime

5.5. Chapter 5 Conclusions 89

Surface and Buffer traps

ˆ Knee-walkout (especially if Vdsq is high and Vgsq < VTO)

Chapter 6.

Modeling of Memory Effects due to

Trapping and Simulation Results

Using standard device models e.g EEHEMT1 available in commercial design softwares, the device behavior can be described accurately for high frequency operations. However, the validity of the models does not cover the description for every operating condition. Thus, the models must be enhanced with descriptions of additional effects like self- heating, charge carrier trapping, gate drain break down, gate diode etc. which cannot be characterized with acceptable efforts by standard I-V and S-parameter measurements. After the measurement and characterization of the charge carrier trapping was discussed in chapter 5, this chapter continues with the main part of the dissertation and focuses on the modeling of memory effects on the device level caused by the charge carrier traps in the device. The purposes of the trap-modeling are:

i). Description of the dependency of the channel current on the operating point due to trapping effects

ii). Description of the dynamic behavior of the device in the frequency range of interest

According to ii), figure 6.1 displays the frequency range investigated for the device listed in chapter 5. For device characterization in the frequency range from 1 GHz to 20 GHz, S-parameters were measured using the pulsed modeling system. For lower frequencies, the network analyser HP8753A with a frequency range from 300 kHz to 2 GHz was used to measure the low frequency dispersion of the output impedance as described in 4.4.2. For the measurements of the effects at frequencies lower than 300 kHz, pulsed time domain measurements were used. However, the minimum current measurement time after the beginning of the pulse is limited to 1 µs by the system related overshoot

[51]. This defines the upper limit of the frequency range for the investigation of the devices in time domain.