Full-chip Level EM Risk Prediction

Based on our discussion in Section 3.2.1, we observe that stress can have a significant impact on the EM reliability of a metal interconnect. We extend our EM modeling to full-chip level design [54]. With TSV-induced stress, Black’s equation is no longer valid to predict the failure time, and we need to solve Eqn. (2.1)-(2.3) using an FEA simulator to estimate the failure time [42]. However, it is very time consuming and impractical to use for full-chip level design. For fast EM estimation of interconnects during routing, we use an EM library. An EM library is a look-up table to get the failure time from inputs such as current density, temperature and stress gradient. We build the EM library by solving Eqn. (2.1)-(2.3) for a simple wire using an FEA simulator. Because we exhaustively simulate T f values with possible combinations of current density, temperature and stress gradient for EM library, fast estimation of the failure time of each wire can be made for full-chip level design. Figure 3.4 shows the flow of our full-chip level EM prediction method.

To predict failure time of interconnects from a given layout, we need to estimate stress gradient value, temperature, and current density, which are inputs of our EM library. For estimating stress level of a certain point with given TSV locations, we use an FEA simulation result for a single TSV and a superposition method to consider multiple TSV effects [47]. From Eqn. (2.2), EM is a function of stress gradient ∇σ, which is the rate of increase of stress. Because we can reasonably assume that a wire is a one-dimensional structure, the direction of the current in a routed wire is a decisive factor to select stress

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Figure 3.4: Flow of full-chip EM estimation of wires for 3D ICs.

gradient vector. For example, if a wire is positioned along the +x direction and current flows in +x direction, stress gradient is interpreted as ∇σ = ∂σ

∂xx.ˆ Temperature is simulated with ANSYS FLUENT with logic power dissipation information, and current density is extracted with a method in [59] from a design exchange format (DEF) file. With stress map, temperature and current density information, failure time of any wire can be predicted with the EM library. All our experiments are performed on a Linux 2.4 GHz processor and our algorithms are implemented in C++. We analyze the impact of TSV on M2 wires near the TSV with 4-die stacked system.

3.4.1 Full-chip EM Prediction for 3D ICs

In Figure 3.5 (b), we plot the result of how hydrostatic stress would vary for vertical wires of given circuits. The result would be different for horizontal wires, however, it can be computed easily using symmetry. We observe that

Table 3.7: Comparison between CST, CT, and ST consideration on EM anal- ysis. EMf is the number of EM failed wires.

ckt #TSV Total wire length [um] EMf

CST CT ST ckt1 934 3.33 × 105 _{503 418 150}

ckt2 1034 3.95 × 105 _{384 294 123}

ckt3 1107 7.95 × 105 _{497 436 98}

ckt4 1336 2.19 × 106 _{713 628 138}

variation in stress, which causes a stress gradient, occurs in regions that are close to the TSVs. To see the impact of different factors of EM, i.e. current, stress and temperature, we perform a full-chip analysis with different driving factor considerations. The results are shown in Figure 3.5 and Table 3.7. In Figure 3.5 (d) we plot the failure map when we consider current, stress, and temperature (CST). The effect of stress and temperature (ST), current and temperature (CT) on EM is shown in Figure 3.5 (e), (f) respectively. We observe that under ST consideration, EM failure is detected especially near the TSV location. Detailed results are shown in Table 3.7. We show the number of TSVs, total wire length, and number of critical wires found using each driving factor consideration, CST, ST and CT.

3.4.2 Effect of Routing Blockage Around TSVs on EM

To improve the EM-reliability of M2 wires in 3D ICs, we add routing blockages around TSVs. The routing blockages ensure that no metal wires go near a TSV location, thus can prevent stress-induced EM failure. The results are shown in Table 3.8. We compare the number of wires likely to fail (EMf)

(a) temperature map (b) hydrostatic stress map (c) current density map

(d) TTF map under C/S/T (e) TTF map under S/T (f ) TTF map under C/T

Figure 3.5: (a) Temperature map. (b) Map of variation of hydrostatic stress for vertical wires. (c) Map of current density. (d) Map of critical wires when considering current, stress, and temperature. (e) Map of critical wires when considering stress, and temperature. (f) Map of critical wires when considering current, and temperature. Circled regions in (c) and (f) show that high current density region correspond to critical locations.

and the wire length. As presented in Table 3.8, adding routing blockages reduces the number of wires that may fail. With routing blockages there are fewer wires that get affected by TSV induced stress, thus we can increase the reliability. The impact on total wire length is less than 1%.

Table 3.8: Impact of routing blockages on EM reliability of 3D IC. EMf is number of EM failed wire and W L is total wire length in µm.

No Routing Blockage Routing Blockage

ckt # Gate EMf WL EMf WL ckt1 14864 503 3.33 × 105 _{435 3.34 × 10}5 ckt2 19895 384 3.95 × 105 _{224 3.96 × 10}5 ckt3 29706 497 7.15 × 105 _{378 7.17 × 10}5 ckt4 103991 713 2.19 × 106 _{587 2.22 × 10}6

3.5

Summary

Electromigration (EM) problems can be more severe and complex in 3D ICs due to TSV-induced stress, higher temperature and current density that affect EM. In this chapter we show that TSV-induced stress can impact on EM reliability of metal wires in 3D ICs. We model EM with TSV-induced stress consideration, and show how TSV-induced stress can affect the EM failure time of nearby metal wires. In addition, we propose a method to perform fast full-chip EM analysis for 3D ICs while considering the effect of TSV stress. Our work shows that TSV-induced mechanical stress can play a crucial role on EM reliability of interconnects in 3D ICs.