DDR2 SDRAM applications may go into a reset state anytime during normal operation.
If an application enters a reset condition, CKE is used to ensure the DDR2 SDRAM de-vice resumes normal operation after reinitializing. All data will be lost during a reset condition; however, the DDR2 SDRAM device will continue to operate properly if the following conditions outlined in this section are satisfied.
The reset condition defined here assumes all supply voltages (VDD, VDDQ, VDDL, and VREF) are stable and meet all DC specifications prior to, during, and after the RESET op-eration. All other input balls of the DDR2 SDRAM device are a “Don’t Care” during RE-SET with the exception of CKE.
If CKE asynchronously drops LOW during any valid operation (including a READ or WRITE burst), the memory controller must satisfy the timing parameter tDELAY before turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM be-fore CKE is raised HIGH, at which time the normal initialization sequence must occur (see Initialization). The DDR2 SDRAM device is now ready for normal operation after the initialization sequence. Figure 80 (page 126) shows the proper sequence for a RE-SET operation.
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CKE
Indicates a break in time scale
tCKE (MIN)
DO
Notes: 1. VDD, VDDL, VDDQ, VTT, and VREF must be valid at all times.
2. Either NOP or DESELECT command may be applied.
3. DM represents DM for x4/x8 configuration and UDM, LDM for x16 configuration. DQS represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, and RDQS# for the appropri-ate configuration (x4, x8, x16).
4. In certain cases where a READ cycle is interrupted, CKE going HIGH may result in the completion of the burst.
5. Initialization timing is shown in Figure 43 (page 87).
bled via the EMR LOAD MODE command, ODT can be accessed under two timing cate-gories. ODT will operate either in synchronous mode or asynchronous mode, depend-ing on the state of CKE. ODT can switch anytime except durdepend-ing self refresh mode and a few clocks after being enabled via EMR, as shown in Figure 81 (page 128).
There are two timing categories for ODT—turn-on and turn-off. During active mode (CKE HIGH) and fast-exit power-down mode (any row of any bank open, CKE LOW, MR[12 = 0]), tAOND, tAON, tAOFD, and tAOF timing parameters are applied, as shown in Figure 83 (page 129).
During slow-exit power-down mode (any row of any bank open, CKE LOW, MR[12] = 1) and precharge power-down mode (all banks/rows precharged and idle, CKE LOW),
tAONPD and tAOFPD timing parameters are applied, as shown in Figure 84 (page 130).
ODT turn-off timing, prior to entering any power-down mode, is determined by the pa-rameter tANPD (MIN), as shown in Figure 85 (page 130). At state T2, the ODT HIGH sig-nal satisfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD (MIN) is satisfied, tAOFD and tAOF timing parameters apply. Figure 85 (page 130) also shows the example where tANPD (MIN) is not satisfied because ODT HIGH does not oc-cur until state T3. When tANPD (MIN) is not satisfied, tAOFPD timing parameters apply.
ODT turn-on timing prior to entering any power-down mode is determined by the pa-rameter tANPD, as shown in Figure 86 (page 131). At state T2, the ODT HIGH signal sat-isfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD (MIN) is satisfied, tAOND and tAON timing parameters apply. Figure 86 (page 131) also shows the example where tANPD (MIN) is not satisfied because ODT HIGH does not occur un-til state T3. When tANPD (MIN) is not satisfied, tAONPD timing parameters apply.
ODT turn-off timing after exiting any power-down mode is determined by the parame-ter tAXPD (MIN), as shown in Figure 87 (page 132). At state Ta1, the ODT LOW signal satisfies tAXPD (MIN) after exiting power-down mode at state T1. When tAXPD (MIN) is satisfied, tAOFD and tAOF timing parameters apply. Figure 87 (page 132) also shows the example where tAXPD (MIN) is not satisfied because ODT LOW occurs at state Ta0.
When tAXPD (MIN) is not satisfied, tAOFPD timing parameters apply.
ODT turn-on timing after exiting either slow-exit power-down mode or precharge pow-er-down mode is determined by the parameter tAXPD (MIN), as shown in Figure 88 (page 133). At state Ta1, the ODT HIGH signal satisfies tAXPD (MIN) after exiting pow-er-down mode at state T1. When tAXPD (MIN) is satisfied, tAOND and tAON timing pa-rameters apply. Figure 88 (page 133) also shows the example where tAXPD (MIN) is not satisfied because ODT HIGH occurs at state Ta0. When tAXPD (MIN) is not satisfied,
tAONPD timing parameters apply.
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tANPD (3 tCKs) First CKE latched LOW
tAXPD (8 tCKs) First CKE latched HIGH Synchronous
Applicable modes
Applicable timing parameters
Synchronous Synchronous or
Asynchronous
Any mode except self refresh mode
Any mode except self refresh mode Active power-down fast (synchronous)
Active power-down slow (asynchronous) Precharge power-down (asynchronous)
tAOND/tAOFD (synchronous) tAONPD/tAOFPD (asynchronous)
tAOND/tAOFD tAOND/tAOFD
CKE
changed with an EMRS set command. MOD (MAX) updates the RTT setting.
Figure 82: Timing for MRS Command to ODT Update Delay
CK#
CK
ODT2
Internal RTT setting
EMRS1 NOP NOP NOP NOP NOP
Command
tMOD
Old setting Undefined New setting
0ns
2 tAOFD tIS
Indicates a break in time scale
T0 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5
Notes: 1. The LM command is directed to the mode register, which updates the information in EMR (A6, A2), that is, RTT (nominal).
2. To prevent any impedance glitch on the channel, the following conditions must be met:
tAOFD must be met before issuing the LM command; ODT must remain LOW for the en-tire duration of the tMOD window until tMOD is met.
Figure 83: ODT Timing for Active or Fast-Exit Power-Down Mode
T1
T0 T2 T3 T4 T5 T6
Valid
Valid Valid Valid Valid Valid Valid
CK#
CK
ODT
RTT
tAOF (MAX) tAON (MIN)
tAOND Address
tAOFD
tAON (MAX) tAOF (MIN)
Valid
Valid Valid Valid Valid Valid Valid
Command
tCH tCL
Don’t Care RTT Unknown RTT On
tCK
CKE
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Don’t Care Valid
Valid Valid Valid Valid Valid Valid
CK
CKE
ODT Address
Valid
Valid Valid Valid Valid Valid Valid
Command
tCH tCL
tAONPD (MIN)
tAONPD (MAX)
tAOFPD (MIN)
tAOFPD (MAX)
Transitioning RTT
Valid Valid
RTT Unknown RTT On tCK
RTT
Figure 85: ODT Turn-Off Timings When Entering Power-Down Mode
T1
T0 T2 T3 T4 T5 T6
NOP
NOP NOP NOP NOP NOP NOP
CK#
CK
Command
CKE
ODT
RTT
tAOF (MIN)
tAOF (MAX) tAOFD
ODT
RTT
tAOFPD (MIN)
Don’t Care Transitioning RTT RTT Unknown RTT ON
tANPD (MIN)
tAOFPD (MAX)
NOP
NOP NOP NOP NOP NOP NOP
CK
RTT
tAON (MIN)
tAON (MAX)
ODT
RTT
tAONPD (MIN) tAONPD (MAX)
Don’t Care Transitioning RTT RTT Unknown RTT On
ODT Command
tAOND CKE
tANPD (MIN)
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Transitioning RTT T1
T0 T2 T3 T4 Ta0 Ta1
NOP
NOP NOP NOP NOP NOP NOP
CK#
CK
CKE
tAXPD (MIN)
ODT
RTT
tAOF (MAX)
ODT
RTT
tAOFPD (MIN) tAOFPD (MAX) Command
Ta2 Ta3 Ta4 Ta5
NOP
NOP NOP NOP
Don’t Care RTT Unknown
tAOF (MIN)
Indicates a break in
time scale RTT On
tCKE (MIN)
tAOFD
T1
T0 T2 T3 T4 Ta0 Ta1
NOP
NOP NOP NOP NOP NOP NOP
CK#
CK
CKE
tAXPD (MIN) Command
Ta2 Ta3 Ta4 Ta5
NOP
NOP NOP NOP
tAON (MIN)
tAON (MAX)
RTT
tAONPD (MIN) tAONPD (MAX)
Don’t Care RTT Unknown RTT On
Indicates a break in
time scale Transitioning RTT
tAOND tCKE (MIN)
RTT ODT
ODT
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All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-times occur.
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