Classification of asynchronous techniques

A digital circuit is asynchronous when there exists no clock signal synchronising the sequence of events [74]. Instead, all asynchronous systems use some form of handshaking mechanism to coordinate the flow of data between elements of the circuit. The most basic and intuitive handshaking signals are request (req) and acknowledge (ack). All asynchronous protocols involve an active element sending a req to synchronise with a passive element, which issues an ack when it is ready to communicate [74]. Depending on whether this communication is sensitive to the

levels or the edges of the handshaking signals, asynchronous protocols are classified as either

4-phaseor 2-phase signalling (Figure 2.6). In 2-phase handshaking whenever a new data value

is available for transfer the req signal transitions. Once the data is received by the passive element, the ack signal transitions resulting in the initiation of a new data transfer. In 4-phase handshaking, only a high level on the req signal results in a data transfer. Once the data transfer is complete, the ack signal is asserted, which causes the req and then the ack to be subsequently deasserted. It is only when the req and ack have transitioned through 4-phases that a new data value can be transferred. In both 2-phase and 4-phase handshaking, the data and control signals are arranged into channels, and ‘data’ flows along these communication channels as a series of entities variously referred to as tokens [37], [41] or wavefronts [38], [75].

Asynchronous techniques may also be classified on the basis of how the data and handshaking signals are combined, into bundled-data systems or dual-rail systems. These two techniques are a trade-off between robustness against timing variations, power and performance. In a bundled-data system, the data is carried in Boolean encoded variables, and the handshaking signals that form the control path are also encoded in binary and bundled together with the data. Appropriate delays are introduced in the control path to delay them as much as the data path signals that implement the logic functions. An advantage of bundled-data systems is that logic is designed as conventional Boolean systems, and this results in circuits that occupy a small area. Bundled-data designs, however, require greater design and timing validation ef- forts to ensure that the timing constraints are met [75]. These systems assume worst case delay in the data path from one register stage to the other. This is similar to a synchronous system where the worst case delay in the clock tree determines the maximum operating frequency. A bundled-data system simply localises the problem by forcing the designer to calculate appro- priate system delay values. If the systems being designed are complex, then designers would be required to compute the critical delays of all the paths in the circuit for the bundled-data technique, something that may be time-consuming and potentially error-prone. Dual-rail sys- tems, on the other hand, encode the request signal into the data signal itself using two wires per bit of information [41]. For each Boolean bit in this systems, there are two wires. One wire is used to signal a logic ‘1’ or true value and the other wire is used to signal a logic ‘0’ or false. N dual-rail pairs may be used to carry an N-bit Boolean value.

Data signals in dual rail circuits also contain the encoded control signals, and therefore per- forming computation with these signals requires one to take extreme care in translating the

functional specifications into circuits. This requirement has led to the creation of different hard- ware templates as follows:

1. Delay Insensitive Minterm Analysis (DIMS) [41], [76].

2. Weak Conditioned Half Buffer (WCHB) [77].

3. Pre-charged Half Buffer (PCHB) [77].

4. Null Convention Logic (NCL) [39].

At the implementation level, correct operation of asynchronous systems is dependent on these hardware templates working correctly under appropriate assumptions of circuit delays lead- ing asynchronous circuits to also be classified based on their delay assumptions as self-timed,

speed-independent (SI)or delay-insensitive (DI) [41]. An exhaustive coverage of the theory

behind these classes of circuits is presented in [76], [78]. Unfortunately, true delay-insensitive circuits are limited in their functionality because of their stringent requirements on wire delays as well. Instead, if it is assumed that that wire forks in the system are isochronic, i.e., the delay of the two prongs of the fork are equal then the result is what is known as quasi-delay insen- sitive (QDI) circuits. Typically, circuits designed using the 4-phase dual-rail approach are all quasi-delay insensitive. QDI systems are an important class of asynchronous systems because they require little timing analysis and can be made to be correct by construction [72].

Achieving delay insensitivity in 4-phase handshaking dual-rail logic systems is typically not possible using ordinary logic gates and flip-flops available in standard cell libraries used to design Boolean systems [79]. Instead, these systems use a fundamental state holding element known as a Muller C-element first introduced by [40]. The C-element and dual-rail encoding technique, both individually and together, have been used in various popular asynchronous circuit design techniques. However, as identified by Fant in [38], they do not represent a coher- ent, easily understandable and adaptable conceptual foundation as they still rely on Boolean logic. It is possible to devise a coherent logic system that completely and unambiguously ex- presses the behaviour of the system without depending on any supplemental temporal infor- mation.