Spread Spectrum
3.1 Principles of Direct Sequence Spread Spectrum
3.3.2 Code Tracking
Code tracking is imperative for continuous reliable data demodulation and is the key to high-resolution distance measurement. The coarse acquisition process described above brings the incoming and local code sequences to within at least
± 1/2 chip of each other, and tracking brings them into almost perfect correspon-dence. One way to improve code synchronization accuracy is to vary the phase of the local code replica until the peak of the correlation tip has been recognized. This method is not particularly systematic, and the peak may not be easily recognized due to signal strength changes due to fading and perhaps motion between the terminals.
A better way is to use a difference signal where a zero level indicates that synchroni-zation has been achieved. One implementation method is the delay lock loop (DLL), shown in Figure 3.19.
The DLL uses two correlators for obtaining an error signal and an additional correlator for data demodulation. The three correlator channels are early (E), late (L), and prompt (P). This arrangement is valid only for a coherent receiver. If there is only frequency lock, and not phase lock, between the carrier and the receiver, two correlators, I and Q, are necessary for each of the channels for a total of six
LPF 90°
IF I data
Q data
VCO LPF
LPF
Figure 3.18 Costas loop BPSK demodulator.
Σ
correlators. In this case, outputs E and L come from envelope detectors, with E=
√
EI2+ EQ2, L=√
L2I + L2Q, and the following description still holds [5]. The terms with the I and Q subscripts are the squarer outputs of the I and Q channels in Figure 3.15.We saw in Figure 3.5 the triangular shape of the correlation function (for an m-sequence), which has straight sides between offsets of±1 bit. A curve based on the output of the envelope detectors of E and L in Figure 3.19 is drawn in Figure 3.20. The acquisition procedure described above brings the matching of the locally generated code phase to within 1/2 bit of the received signal code; that is, to approximately one-half the height of the triangle in Figure 3.20. The early and late envelope detector outputs are the result of correlation of local code generator signals with phases that are 1/2 chip earlier and later than the code generator that gives the prompt output. These signals can be expressed as [1]:
VP= K ⭈
|
T ⭈1 t冕+ Tt g(t)⭈ g(t + ) dt|
VE= K ⭈
|
T ⭈1 t冕+ Tt g(t)⭈ g冉t++T2c冊 dt|
(3.15)VL= K ⭈
|
T ⭈1 t冕+ Tt g(t)⭈ g冉t+−T2c冊 dt|
where g(.) is the code sequence,is the phase difference of the prompt replica, Tc is the chip period, and K is an amplitude factor. When the prompt signal is synchronized, that is, is on time, E is 1/2 chip early and L is 1/2 chip late. The
−1 0 1 Figure 3.20 Correlation curve from envelope detector.
correlation curve is symmetrical, so the error signal is zero and the VCO frequency is not changed. However, if the prompt lags the received signal, the error line is positive and the VCO increases the replica rate to try to catch up. Similarly, if the prompt leads the incoming sequence, the error signal is negative and slows down the replica. The error signal is given by [5]:
error=E − L
E + L (3.16)
which cancels out the amplitude factor K. A normalized error signal curve, along with the prompt curve, is shown in Figure 3.21. We see from this curve that the linear portion in the center is less than 1 bit wide. This indicates that to prevent the code synchronization loop from losing lock at the edges, the acquisition should bring the code phases to closer than one chip of each other. In an alternate configura-tion, the error signal is based on power detection of E and L :
errorP= E2− L2
√
E2+ L2 (3.17)−2 −1.5 1 −0.5 0 0.5 1 1.5 2
−1
−0.5 0 0.5 1
Prompt Error
Chips
Figure 3.21 DLL Discriminator output curve and prompt output curve.
The relevant portion of this curve, between the peaks, is 1 bit wide as desired but is not perfectly linear [5].
The rate of VCO correction must be slow compared to the correlation integra-tion period T. The rate is determined by the gain of the error feedback loop. Loop stability can be tightly controlled if a phase increment is introduced to the VCO during each integration period. A small increment can be inputted, positive or negative, after reading the error signal, and then repeated after each progressive integration period until the error is zero.
Instead of a VCO, a numerically controlled oscillator (NCO) is preferably employed. The NCO is a digital frequency synthesizer that allows exact frequency or phase increments, and its output is related to the system clock. Figure 3.22 is a block diagram of an NCO. It shows both cosine and sine digital outputs but when quadrature signals are not needed, the sine output need not be included. The inclusion of digital to analog converters followed by antialias filters makes what is often referred to as a direct digital synthesizer (DDS).
The NCO operates as follows. The phase accumulator is a binary counter with N bits that is incremented periodically by a master clock of frequency fS. The output of the phase accumulator is plotted in Figure 3.23(a). On each clock pulse, the contents of the frequency register, ⌬, are added to the accumulator. The period of the generated frequency f0is determined by the accumulator overflows.
The output frequency is
f0=⌬⭈ fs
2N (3.18)
The phase of the output is determined by the contents of the phase register.
The linearly stepped digital accumulator output can be changed to a digital sine or cosine output using look up tables in ROM. These outputs in turn are inputted to digital to analog converters, followed by antialias filters, to produce analog signals. Figure 3.23(b) shows the sine output before filtering. The output frequency is generally limited to 40% of the sampling frequency. The minimum frequency and frequency increments are f0/2N and possible phase increments are 2/2N. When the output of the NCO determines the chip rate, the phase increment as a fraction of a chip period determines time of flight increments and consequently distance resolution, which is
Figure 3.22 Numerically controlled oscillator (NCO).
(a)
Figure 3.23 NCO output signals: (a) at output of phase accumulator, and (b) at output of sin ROM.
␦d= c
f0⭈ 2N (3.19)
for a one-way measurement. c is the speed of light. For example, a chip rate of 10 Mcps and an NCO with 24-bit accumulator gives a distance resolution of 2 microns!
Synchronization time increases as resolution increases (smaller numbers) so attempts to get the stated best resolution are not practical. Also, noise, interference, multipath, and relative movement as well as timing inaccuracies make the actual accuracy of a DSSS distance measuring system much lower than that implied by the maximum resolution.