The Octa is wire-bonded to a 0.5 mm thick PCB for connection to a multichannel read-out DAQ system. The DAQ system proper is comprised of the read-out electronics, which has been described elsewhere [190], the graphical user interface (GUI), which was coded in C++ using a Qt (Nokia) application and whose original version has been described elsewhere [191], and the firmware.
Recent updates introduced to both the firmware and the GUI are described below, after an introduction on their original implementation.
Figure 15. Snapshot of the Octa data acquisition system (DAQ). Starting from the left side, the 4 boards with 2 AFEs each. Plastic case containing the FPGA and associated circuits. Three ports are visible on the case: that for the USB link (for data transmission to/from PC), that for the power supply and that for the coaxial cable (for linac trigger signal acquisition).
The read-out electronic system (Figure 15), is based on a field-programmable gate array (FPGA) Xilinx Spartan 3, 4 analogue-to-digital converters (ADCs) and 8 commercially available analogue front-end (AFE) AFE0064 (Texas Instruments) chips [192].
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The system was devised so that the Octa could be used as a dosimeter for linacs. These machines deliver a pulsed radiation beam, with a fixed repetition rate in the range from 200 Hz to 400 Hz, a parameter characteristic of each linac model [84]. The pulse is triggered by an electron gun and lasts for 3 µs to 5 µs.
The user is required to have knowledge of the electron gun trigger frequency and set it in the GUI. Parameters and commands set by the user in the GUI are read and used by the FPGA, which handles the data transfer to/from the PC through an Opal Kelly XEM3001 integration module. The FPGA handles also the synchronisation between AFEs and the linac trigger, acquiring the latter via a coaxial cable.
A firmware, which configures the FPGA and defines the input/output (I/O) addresses used for communication with the PC, must be loaded in the GUI at device turn-on.
The AFE performs two functions, ‘Integration’ and ‘Data Read’ for each pulse acquisition (see Figure 16 and Figure 17). The integration function consists of two compulsory phases, ‘Reset’ and ‘Integration’.
The reset phase is initiated by closing the reset switch (IRST rising edge), setting each amplifier output to the reset-level. At the end of this phase, the output V is measured to get the reset sample. This phase lasts for 70 µs using a 2 MHz FPGA clock. Because the linac trigger frequency is known and constant, the reset sample is acquired during the 70 µs immediately before the expected arrival of the trigger signal. The reset phase ends with the SHR rising edge.
Starting from 30 µs before the expected linac trigger, and for the duration of the beam pulse, the charge resulting from electron-hole pairs generated in the device owing to the incident radiation is collected by a capacitor. The 30 µs offset was introduced to ensure that the beam pulse would turn on during the integration window.
At the end of this integration phase, an output sampling command triggers the simultaneous sampling of the 512 channels. The collected charge is converted into a voltage level V, corresponding to the signal sample, which is the output of the amplifier of each channel:
V = QC (4.1)
The difference between signal and reset samples is then sent to the ADCs. In this way, the effects of electronic noise and leakage current are minimized. Data transfer (labelled data read in Figure 16, Figure 17) is performed during the reset phase and is triggered by the STI rising edge. This description illustrates the original working release of the firmware (Figure 18).
These firmware settings were designed so that the DAQ could work with linacs, such as the Varian Clinac® iX system and the Elekta Axesse™, which have a constant electron gun
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frequency. In modern radiotherapy, novel treatment machines used to deliver small radiation fields such as the Varian TrueBeam™ STx, have an electron gun frequency which is non- constant and varies during treatment delivery depending on beam energy and dose rate. Ever more often, they are also used to deliver flattening filter free beams, which are characterized by higher instantaneous dose rates. These may result in the detector response being saturated.
To deal with these issues and allow for the DAQ to work with novel linacs, two updates where introduced to the original firmware version Top_11_512ch, as listed in Table 4.
A first update (Top_512ch_15MHz) was devised to disentangle the acquisition from the constant trigger frequency requirement. This was achieved by synchronizing the IRST rising edge with the trigger signal, with the user no longer required to set the trigger frequency in the GUI (see Figure 19). The compulsory reset phase is performed in 8.6 µs using a 15 MHz FPGA clock (the maximum allowed by the manufacturer). The INTG rising edge immediately follows the SHR rising edge. The data transfer is performed immediately at the end of the integration phase. This firmware was validated against the original version by comparing the acquisition of a 2 cm square field with a 6 MV medical linac, all other measurement conditions being equal.
A second update (MP_512_IToffset) was conceived to prevent the detector response from being saturated at high instantaneous dose rates. An offset, a constant parameter set by the user in the GUI and applied to each beam pulse acquisition, was introduced. The beginning of signal integration is delayed for a fixed time after the arrival of the trigger signal (see Figure 20). This results in an overall lower integrated charge.
A third update which merges the previous two firmware updates is also available.
Table 4. List of available firmware and their description.
Firmware name Description
Top_11_512ch Original working release
Top_512ch_15MHz Reset procedure is performed with FPGA clock at 15 MHz MP_512_IToffset Offset delays start of integration window
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Figure 16. For each beam pulse acquisition, the FPGA performs two functions, ‘Integration’ and ‘Data Read’. Signals IRST, SHR, SHS, INTG, CLK control 'Integration Function' and STI, CLK control 'Data Read Function'. EOC is a device output and a low level on the EOC pin indicates a data read is in progress. IRST rising edge starts the ‘Reset’ phase which ends with SHR rising edge. IRST rising edge resets the integrator capacitors on rising edge of this input. STI rising edge resets the channel counter. SHR rising edge samples the 'reset' level of the integrator output. INTG filters bandwidth control for Signal sample (SHS). SHS rising edge samples 'signal' level of integrator output. STI falling edge enables data transfer. CLK device serially outputs the analog voltage from each integrator channel on every fourth rising edge of CLK [192].
Figure 17. Each integrator has a reset (IRST) switch which resets the integrator output to the 'reset-level'. The input current is integrated while this switch is open. There are two sample and hold circuits connected to each integrator output. SHR samples integrator reset-level output and SHS samples integrator output post-integration of signal. The device subtracts the SHR sample from the SHS sample. The difference is then available as output in a differential format [192].
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Figure 18. Original firmware settings. The reset procedure is performed in 70 µ𝑠𝑠 before the expected trigger signal (fixed frequency set by the user in the GUI). Data transfer (of previous beam pulse acquisition) is carried out during the reset window. Integration (of current beam pulse) starts (INTG) 30 µ𝑠𝑠 before the trigger. Yellow signal is trigger signal.
Figure 19. Firmware update ‘Top_512ch_15MHz’. At trigger signal, the reset procedure is performed at 15 𝑀𝑀𝑀𝑀𝑀𝑀 in 8.6 µ𝑠𝑠. At its completion, integration starts (INTG). 15 MHz is the maximum clock frequency allowed by this FPGA design. Yellow signal is trigger signal.
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Figure 20. Firmware update ‘MP_512_IToffset’. The reset procedure is performed in 70 µ𝑠𝑠 before the expected trigger signal (fixed frequency set by the user in the GUI). Data transfer (of previous beam pulse acquisition) is carried out during the reset window. Integration (of current beam pulse) starts (INTG) after the trigger by a fixed user-defined time window (offset). Yellow signal is trigger signal.
4.4 A touch of Monte Carlo