Comparing Different Input Voltage Levels

At the beginning of this section, it was discussed that two amplitudes were tested; one being 9dBm and the other 11dBm. In this part of the section we will look at the same SNDR, SNR, THD, and SFDR plots comparing the measurements of the two input amplitudes. Figure 4.3.5 shows the relationship between SNDR and reference capacitance. SNDR between both measurements are approximately the same. The trial with lower amplitude shows slightly better SNDR, especially between 10nf and 1µF .

Figure 4.3.6 shows the SNR characteristic curve. This curve shows that the larger am- plitude has a better SNR ratio. This is because the noise floor remains relatively constant between the two measurement trials, thus higher signal power would improve the SNR. At capacitances under 1µF , the distortion terms beyond the fifth harmonic begin to grow ex- ponentially. Since they counted as noise terms, the SNR characteristic shows the expected S-shape. Since the harmonics are proportional to signal power, the SNR of the two curves begin to converge at lower capacitances.

Figure 4.3.7 shows that the two THD curves are on two distinct levels. Both remain relatively constant across the reference capacitance range. This shows that although the first few harmonics are independent of reference capacitance, they are dependent on the amplitude of the signal. This separation does not coincide with the implications of Figure 4.3.3, which shows an inverse relationship between amplitude and THD. As previously discussed, it was known that a higher amplitude input signal set directly on the signal generator led to a higher distortion. However, when the distortion of the signal generator is held constant, decreasing the signal amplitude through filtering causes another source of distortion to increase in power. These distortion terms are mainly limited to the first four harmonics.

Figure 4.3.8 shows that smaller amplitudes will achieve better SFDR. This indicates that although the signal power is lower, the power in the largest harmonic spur decreases even more; which leads to an improvement in SFDR. This finding does not match up with the results illustrated in Figure 4.3.4, which shows the SFDR relationship using constant amplitude set on the signal generator. However, in this case, the change in SFDR implies that the additional distortion power that causes the curves to separate originates from the signal generator itself.

Figure 4.3.8: Measured SFDR versus Reference Capacitance for 9dBM and 11dBm Signals

The measured results presented in this chapter show how the performance of a real ADC varies with different bypass capacitors, or reference capacitances. In the analysis presented in Chapter 3, the bypass capacitor, voltage reference circuit and internal DAC are investigated. However, the analysis ends with a single switching cycle. One measurement taken with con- troller board contains 217 _{samples. This implies that the AD7276 completed approximately}

220 _{switching sequences per measurement taken. Thus, it would be too time consuming to}

complete analytic results to compare with the measured results. Instead, the analysis is used to generate a model programmed in Matlab to generate simulated results. These simulated results are presented and compared to the measured results in the next chapter.

Chapter 5

Simulations

Based on the analysis done in Chapter 3, a model written in Matlab was created. Simulations were conducted using this model to recreate the results seen in the experimental results. The complete code can be found in Appendix H. The AD7276 is a real Successive Approximation ADC (SAR-ADC) with many practical limitations. These limitations include noise, parasitic capacitance, INL and DNL errors, all of which affect the ADC’s performance. Since the magnitude of their effect on the performance is unknown to the user, they were not originally considered in the when simulating the simulated sinusoidal signal and the model. Once the ideal simulations were used to generate results, these limitations were identified through comparing the simulations to the measured results.

5.1

Creating a Practical Model

Though the analysis describes how the model should behave, to generate comparable sim- ulated results to the experimental results some additional features were added. Firstly, additional white noise was added to the signal input and output such that the noise floor was at the same level as seen in measurements. Secondly, a parasitic capacitance was added in parallel to the reference capacitor. This was required to shape the response such that the distortion would saturate as capacitance decreases. Without this parasitic capacitor, the dis- tortion would continue to increase in power indefinitely. These added non-ideal components make the simulated model more complete, making it generate realistic, practical results. Additionally this shapes the curve without the need for adding additional distortion terms. Figure 5.1.1 shows a comparison of a SNDR characteristic curve of an ideally realized model to that of the practical results.

100−10 10−9 10−8 10−7 10−6 10−5 10−4 20 40 60 80 Capacitance (F) SNDR (dB) SNDR vs Reference Capacitance Initial Simulations Measurements

Figure 5.1.1: Simulated SNDR using an Incomplete Simulated Model (Black) versus Mea- sured Results (Grey)

Key factors must be added to the model such that the results coincide with the measured results. Some of which would be noise, parasitic capacitance, and charge restoration of Cref.

The noise level for an ideal 12-bit SAR-ADC is derived from Equation 5.1.1 to be at -122dB. It should be noted that N is the resolution of the ADC, and M is the number of bins in the FFT. The Measured results show a noise floor near -100dB, so white noise was added to the input and output sinusoidal signal to model the added noise of the circuit.

N oiseF loor = 6.02N + 1.76dB + 10log(M/2) (5.1.1) The AD7276 includes a non-ideal charge redistribution DAC. However, there is no indi- cation of how the internal circuitry is actually implemented. For the purpose of modelling the DAC, many assumptions are made that are incorrect and do not reflect the actual circuit inside. This is done to isolate the non-ideal behaviour being investigated from other circuit dependent issues, and also keep the model simple. In the simulated model, an ideal binary weighted charge sharing DAC was used. Additionally, many assumptions and approxima- tions were made concerning the unit capacitance value for the switched-capacitor array, and the parasitic capacitance previously described. The unit capacitance defines the value for the array capacitance, Ca. Equation 5.1.2 governs how Vref changes, thus by manipulating the

ratio Ca

Cref and the parasitic capacitance, the simulated characteristic curve can be shaped.

(Cp) values used for the model are not approximations of the actual values of capacitances

in the real ADC. These values were determined for the sole purpose of curve fitting. The analysis done in Chapter 3 shows that the reference errors were proportional to the ratio of the capacitances, not the values of the individual capacitances themselves. Thus, what can be said is that the ratio Ca

Cref+Cp is approximately ≈ 976.5 × 10 −6_. Vref,new =  1 − [y(x − y) + z(1 − x + y − z)] Ca Cref  Vref (5.1.2)

Another assumption being made is how Vref is restored once charge is pulled off of Cref.

Vref is decreasing during each switching sequence, however this cannot continue indefinitely.

Charge must be pulled from the voltage reference circuit to ensure long-term stability. Many mechanisms were investigated for applicability in the simulated model. Because the purpose of the simulated model is to maintain simplicity in the analysis, only linear and first-order systems were investigated. In one attempt, a constant current source was used to restore Vref. Another attempt involved using a RC first order charge restoring system, where the

time to charge the reference capacitor is governed by the RC time constant. These non-ideal charge restorers create a correlation between sampling frequency and the distortion. If there is not enough time for the charge to be restored, then distortion seen at the output should increase as the sampling frequency increases. According to the AD7276 timing analysis, between each sample exist empty clock cycles. This would theoretically allow enough time for Vref to be restored between samples. Furthermore, using charge restoring mechanisms

such as the RC system, or simply adding charge proportionally to the difference between Vref

and the ideal supply, implies that the reference performs worse, or slower, at higher reference capacitance. According to the measurements, this phenomena is not seen, which implies that sufficient charge is added in between samples to allow Vref to be fully restored. Lastly, since

the sampling rate is held constant in this analysis, within a single sample the associated error is relatively constant for each measurement and simulation results. Through simulation, it has been verified that each of the charge restoring mechanisms tested do not show significant differences in their outputs. Thus, to maintain simplicity in the simulation, Vref is simply

restored back to its original value after each sample.

Specifically for the dynamic testing section of this chapter, four different inputs were used. The frequencies and amplitudes of these ideal sinusoidal inputs are the same as those shown in Table 4.2.2. Additionally, the same sampling rate of 20280590 samples per second and 217

samples taken per FFT were used. This was done to provide comparable plots to those seen in Chapter 4.

5.2

Dynamic Testing

Dynamic testing is used to quantify the distortion seen at the output of the simulated ADC when it is fed an ideal sinusoidal signal. The dynamic specifications taken from the simu- lations are defined such that they are comparable to the measurements taken in Chapter 4. The dynamic measurements begin with creating of a single tone FFT from the digital output of the simulated ADC.