Comparison to Prior LT Designs

SCREW builds upon several prior LT microarchitectures, with an emphasis on energy efficient slice- out. At a high level, SCREW is similar to WIB in that instructions are allocated a slot in the slice-buffer at dispatch in program-order. This is in contrast to architectures like CFP and BOLT which pseudo-execute instructions through the pipeline to release scheduling resources in execution- order (i.e. after dependents wake up) before slicing out from the ROB in program-order.

Compared to WIB, SCREW’s slice-out and execution mechanisms are much more efficient. In a WIB processor, instructions are issued only from the issue queue but are stored in both the WIB (slice-buffer) and issue queue. An instruction in WIB is “sliced” and removed from the issue queue

if it depends on a load-miss. The issue queue is informed of the cache-miss after it occurs, and the instructions waiting on the load destination register are removed from the queue. These instructions are re-injected into the issue queue from the “waiting instruction buffer” when the load data returns. This mechanism is inefficient at dealing with chains of loads. A stream of instructions can ping-pong between the WIB and issue-queue if a series of loads are sliced out where loads in the dependency chain miss in the cache. In SCREW, instructions are dispatched into only one structure—the issue queue for loads predicted to hit in the cache and their dependent instructions, and the in-order queue for instructions depending on loads predicted to miss the cache. Unlike WIB, BOLT, and CFP, instructions can only issue from the structure they were dispatched into; there is no duplication of instruction data between multiple structures, no thrashing between queues where instructions are re-injected and re-sliced, and no redundant dispatch or issue.

At the tail end of the pipeline, SCREW is conceptually similar to a BOLT [35] and CPR [2] processor. When the head of the ROB is blocked from retiring because it is a load instruction waiting for a cache miss to return, a BOLT processor will create a checkpoint and speculatively retire “poisoned” instructions which depend on the miss. SCREW performs the same actions, but has a different organization and slice-out flow. In BOLT, instructions dependent on the load-miss are identified through “poison” bits which propagate from the load missing at the head of the ROB backwards to dependent instructions in the issue-queue. Poisoned instructions are removed from the head of the ROB and issue-queue, and are placed instead into a “slice-buffer” which functions as a secondary ROB. This slice-buffer ROB looks similar to the ROB style found in older Pentium processors—instead of storing only instruction meta-data and register pointers, the BOLT slice- buffer ROB stores both the instruction and the data value of a ready input operand. This allows BOLT to free registers that are consumed by poisoned instructions at the cost of a larger ROB and the cost of transferring the data.

SCREW enters a speculative retirement regime when the ROB is blocked by a load miss with a similar checkpointing mechanism. SCREW has identified loads likely to miss and has already tracked their dependents, so no ‘slicing’ or transferring is necessary. The dependency matrix also

tracks dependency chains for loads predicted to hit. If this prediction is incorrect, SCREW can still checkpoint the register state and enter a speculative-retirement mode because each instruction is tagged with the load chains they depend on. An instruction dependent on a load incorrectly predicted to hit can be added to a checkpoint prior to finishing execution. Instructions independent of the load miss will not be added to the checkpoint until they finish execution normally.

Unlike BOLT and CFP, SCREW does not need to copy instructions dependent on the load-miss from the ROB into the slice-buffer, as they will have already been placed there at dispatch due to the load prediction mechanism at the front-end of the pipeline. SCREWs speculative-retirement procedure also requires less energy than in BOLT and CFP. SCREW only needs to remove a sliced instructions instructions entry from the re-order buffer when speculatively retiring it; SCREW does not need to perform a value copy because it does not release these registers, nor does SCREW need to propagate poison, because the dependency chains are tracked at the front-end of the pipeline. SCREW’s FIFO queue more closely resembles modern re-order buffers with register pointers, rather than an older Pentium style buffer which stores the full data value [57]. This organization eliminates a register-read and value-copy operation, at the cost of potential decreased performance, as destination registers are kept occupied while instructions are waiting in the FIFO buffer for their load to return. While this does prevent registers from being reused for ‘active’ instructions, rather than ‘waiting’ instructions, this scheme does lend itself well to power-gated and drowsy modes for registers described earlier in Chapter 4.

SCREW reduces the energy cost of latency tolerance by replacing a reactive slice-out approach— poison-execution/value copy/re-dispatch/re-issue—in CFP and BOLT with pro-active dispatch ap- proach. SCREW steers instructions likely to be miss-dependent into a FIFO, avoiding the issue queue entirely. SCREW also takes a different approach to scaling the physical register file. SCREW’s spec- ulative retirement is re-designed to release the physical registers of miss-independent instructions and eliminates the value-copy operations prevalent in BOLT. There is no re-renaming or re-dispatching into the issue queue after the load returns, saving energy and reducing complexity.