Figure 6.5 shows the Network Interface RTL model written in Verilog HDL. It has a modu- lar implementation that follows the architecture discussed above. Timing information about the pipeline stages has been obtained from this model. Furthermore, the pipeline changes allowed the extraction of conservative timing latency of three and two stages pipeline archi- tectures as well as of a single cycle NI architecture.
FIGURE6.5: Verilog HDL modules inclusion
80 Chapter 6. Network Interface (NI)
Figure 6.5 shows the Verilog HDL modules inclusions. In sub-module noc2wb all the NoC-to-Node pipeline is implemented and in sub-module wb2noc all the Node-to-NoC pipeline is implemented. The decoupling of the two pipelines makes them easy to extend and opti- mize. The model can be adapted for other bus interfaces simply changing the wrapper mod- ules.
Figure 6.6 show the finite state machine of the NI controller, which show how the data packet travels through out the network interface.
6.4.1 The Packet Buffer
The Packet Buffer represents a temporary storage for incoming packets from the bus that are waiting to be injected into the NoC. It is composed of several buffers, each of them can store the longest packet of the network. When a message is received by the WISHBONE Slave Wrapper, it is packaged and stored in a free buffer. If no free buffer is available, the WISHBONE Wrapper stops the communication and will restart it only when space is freed. In this buffer the packet waits for virtual channel allocation and transmission of flits. Figure 6.7 show the block diagram of packet buffer generated by Xilinx.
FIGURE6.7: Symbol of Packet Buffer Module
6.4.2 The Virtual Channel Allocator
Traditionally, the Virtual Channel Allocator stage contains the critical path of the router pipeline. In the Network Interface this module is considerably less complex since a sin- gle output port is available.
An N : 1 arbiter is used for each virtual network. Each arbiter receives N requests, where N is the maximum number of packets that can be stored in the Packet Buffer, and allocates an available virtual channel only for one of them, if any. Note that this architecture does not underutilized the link bandwidth, since even if only one it per cycle wins the VA stage, this it will be transmitted on the only link available. Figure 6.8 show the block diagram of Virtual Channel Allocator.
FIGURE6.8: Symbol of Virtual Channel Allocator Module
6.4.3 The Link Allocator
The Link Allocator is an arbiter N : 1, where N is the maximum number of packets that can be stored in the Packet Buffer. It receives the request transmission from the its that have already won the VA stage. Only one of them can win and use the link to the router in the next cycle. The Link Allocator architecture is same as the architecture of the Arbiters as shown in figure 6.9.
FIGURE6.9: Symbol of the Link Allocator of Module
6.4.4 The WISHBONE Wrapper
The implemented NI exposes the standard interface of a WISHBONE master and a WISH- BONE slave IP, since it must act as a slave and a master from both the bus and the NoC perspective. Internally, to keep logically separated the reception and transmission of a mes- sage, the Slave Wrapper always receives messages, and the Master Wrapper always sends messages. This implies that the Slave Wrapper must receive the reply of a slave node to a read transaction started by the NI MasterWrapper, and the MasterWrapper must transmit the reply of a read transaction for the NI Slave Wrapper. Figure 6.10 shows in details the wrapper interactions. The rest of the section discusses every possible transaction to clarify the implementation. When a packet is received, if it is a write transaction, it is simply sent by the Master Wrapper on the bus, since no reply must be sent back. If the packet contains a read transaction, the MasterWrapper starts the transaction and the reply is stored in the Slave Wrapper. The Slave Wrapper does not allow the Master to start a read transaction if no space is available in the Packet Buffer.
82 Chapter 6. Network Interface (NI)
FIGURE6.10: Wrappers architecture
FIGURE6.11: Wrappers module generated by Xilinx
When the NI acts as a slave two cases are possible. If it serves a write transaction, the Slave Wrapper receives the message and injects it in the NoC. If it serves a read transaction, the Slave injects the request in the NoC and saves an entry in the On-the-Fly table, with the
information of the waited message. When the Master receives a packet that contains the reply for the transaction, it replies for the Slave and closes the transaction. This kind of architec- ture is required to overcome the absence of split transaction in the WISHBONE bus. If this feature had been available it would not be need of the table, since in this case a master always sends and a slave always receives messages. Figure 6.11 shows the Block Diagram generated by the software itself.