Concept of the test board

The very rst decision was to reuse the existing infrastructure which is cur- rently used in the ALICE experiment, described in [AT]; in the ALICE TPC, the front-end of this infrastructure is the RCU board, which connects with several Front-End Cards (FECs): the S-Altro test board must therefore be mechanically and electrically interchangeable with a FEC and compatible with the RCU.

After this, the main requirement for the test board is a great versatility, in order to allow testing of many features of the S-Altro. Moreover, the tests must be possible for both packaging options (PGA and QFP); therefore, the test board has a duplicated structure, where the sockets for both packages are present and each one has potentially all the electrical connections needed for the tests; eventually, using shorting or opening elements, the user chooses whether to test the PGA or QFP chip.

The diagram of the Test Board is depicted in gure 5.1. Apart from the

ADC Test Input Sinewave

PulseGeneratorClock

Power supplies

1.5V 10% PASA 1.5V 10% ADC Analog 0.8-1.5V ADC Digital + Digital Core

2.5V 10% Digital Pads RCU (FPGA) T ra n s c ei v e rs T ra n s c ei v e rs Vref ADC 0.25V 0.75V 1.25V S-ALTRO Clock Distribution and delay generator Board Controller (FPGA) 12b ADC Voltage divider

Ext Pulse Generator ``

x16 40 12 Interface control S-ALTRO BUS 54 40 12 C on fig ura tio n PA SA B ia sD eca y AD C B ia s Input 0 Input 15 Scl k C lkAu x PA SA O ut Aux ADC clk Rdoclk Sclk TEST BOARD 12 PA SA S hu tD ow n ScanChainCtrl 3 jumpers Configuration ADC ShutDown ExtGeneratorTrigger

Power supplies ShutDown

Figure 5.1: Diagram of the test board, showing also the connection to the Readout Control Unit (RCU) board.

this is an FPGA which controls all the programmable functions on the board, and also the communication between the S-Altro and the RCU.

This communication is physically implemented by seven bidirectional transceivers. The BC sets the enable lines of the transceivers either in in- coming, or outgoing direction, or in high impedance. In particular, it en- ables the outgoing data ow when the S-Altro asserts the DOLO_EN and TRSF_EN lines, indicating that it wants to write data into the 40bit bus. The transceivers are also used when reading or writing the conguration registers of the BC, or when sending commands to the BC itself.

The supply voltage to the various components on the board is provided by some linear Low DropOut (LDO) regulators. Some of these regulators have shutdown pins, each controlled by a signal line coming from the BC. Therefore, by writing appropriate values in some BC registers, it is possible to implement shutdown mode and power pulsing schemes.

The regulators for the power domain of the PASA, the ADC Analog and the ADC Digital can be shut down completely. The regulator for the DSP domain is congured in such a way, that its output can be reduced by the BC to a variable value as low as 0.8V; this minimum value is due to the requirement of keeping the contents of the memory, discussed in section 5.1. Regulators which supply the S-Altro have some shunt resistors, in order to measure their currents; this is used to monitor and plot the power consump- tion of the chips.

Two clocks arrive to the test board from the RCU board: the readout clock as single-ended and the sampling clock as a dierential signal.

The readout clock is buered by a commercial Integrated Circuit (IC) and delivered to the S-Altros and to the Board Controller; the BC has the possi- bility of shutting down the readout clock branches which go to the S-Altros, thus removing their clock.

The sampling clock is distributed by a more complicated IC, which delivers up to six single ended clocks, two of which can be delayed with respect to the other four. The BC controls which of these six clocks are enabled and which are o; this feature can be used in power pulsing tests. The reason why this particular IC was chosen is that the delayed clocks can be used as S-Altro ClkAux, in order to delay the clock of the DSP with respect to the ADC clock, as explained in section 4.6. The other outputs of this IC can be routed to the BC, to the S-Altro Sclk, to an on-board ADC and to an o-board instrument (after conversion to TTL logic level).

This commercial clock distribution IC provides external clock in CMOS logic at 2.5V; the sampling and auxiliary clocks of the S-Altro are in a 1.5V do- main. Therefore level shifting of the clocks is necessary, and two solutions are implemented on the test board: a resistive divider, and level shifting through

a commercial IC. The performance of the commercial IC, in terms of jitter and integrity (shape) of the clock signal was to be evaluated, and therefore the resistive divider was kept as an option in case of bad results from the IC; during the tests, the chosen commercial IC proved a good solution and did not introduce any problems.

At the analog inputs of the S-Altro, an array of 0Ω resistors and capaci- tors allows the choice of the input signal. The input can either come from an external pulse generator (through a series capacitor which emulates the de- tector capacitance) or from a detector cable; in the latter case, the connector is of the same type used in the ALICE TPC, for compatibility.

The external pulse generator has to be synchronized with some internal signals, i.e. the sampling clock. Therefore, two TTL level shifters provide trigger outputs for external devices; these two outputs are driven by the BC and by the clock distribution IC. During tests, the external pulse generator is triggered by the BC, using the Level-1 trigger, which is synchronized with the sampling clock; in this way, the pulses are always sampled with a chosen phase, which allows, for example, to easily measure the maximum of the pulses; according to simulations, the jitter allowed to the trigger signal is 1.5ns when the shaping time of the PASA is 120ns, and 100ps with shaping time 30ns, for 0.5 LSB resolution.

As shown in section 4.7, channel 15 of the S-Altro has the option of sending o-chip the dierential output of the PASA and of providing an external dierential input to the ADC. Therefore, on the test board there are connectors for an external waveform generator, which could drive the ADC test inputs. Moreover, there is an external ADC, which can digitize the outputs of the PASA in channel 15; this external ADC was chosen with 12 bits of resolution and 65MHz of maximum sampling frequency, so that it is not the bottleneck of the measurements.

The Board Controller will save the 12bit output of the external ADC in some internal memory, when instructed to do so; the memory of the Board Controller is then readout by the RCU. The same two-step procedure applies during the test mode TSM, described in section 4.7, when the Board Con- troller saves the raw data from the S-Altro, and subsequently transfers these data to the RCU.