Conclusion 149

In this research, model equations for surface potentials for non-ballistic and ballistic CNT-FETs are presented. The current transport equations for non-ballistic CNT- FETs are summarized, which were derived in one of our earlier work [91]. Based on these equations, dynamic model equations for linear and saturation regions of operation of CNT-FETs are derived. The current transport equations for ballistic CNT-FETs are also described. The modeled I-V characterizations are in agreement with the experimental results and the model proposed by Akinwande et al. [116]. By using the static and dynamic models for non-ballistic CNT-FETs, we have studied performances of some basic CNT-FETs circuits such as the inverter and ring oscillator. The simulation results of ring oscillator frequencies are fairly close to the experimental data.

We have proposed a simple method to develop a transmission line model for metallic carbon nanotube (CNT) interconnects using classical electrodynamics. The effective conducting electrons in carbon nanotubes are modeled as one-dimensional fluid considering electron-electron repulsive interactions. This method provides an equivalent circuit for analyzing the SWCNT interconnect as a transmission line. Damping effect is observed in SWCNTs due to its high resistance. It is observed in SWCNTs below 1 MHz for lengths less than 1 µm, and above 100 MHz for length longer than 100 µm. Thus, short length SWCNTs (< 1 µm) can be used above 1 MHz. Damping thus limits the usable frequency bandwidth since it is dependent on the length. Calculations of group delays show that CNT interconnects can also be used above 200 GHz for short interconnects (< 1 µm) and 10 GHz for long interconnect (> 100 µm). Study of S- parameters suggests consideration of impedance matching at the input and output to minimize losses due to reflections for longer SWCNT interconnects.

Models for CNT interconnects, which include MWCNT and SWCNT bundle are discussed based on one-dimensional fluid theory. The one-dimensional fluid model can be applied to CNT interconnects using low resistance contacts in current low-voltage

nanometer CMOS technologies. The applicability of MWCNT and SWCNT bundle as interconnect wires for next generation design of integrated circuits has been explored theoretically and compared with Cu interconnects in 22 nm technology node. Results of the one-dimensional fluid theory for SWCNT interconnect extended to MWCNT and SWCNT bundle interconnects show that MWCNT and SWCNT bundle interconnects have better performance than the Cu interconnects. MWCNT and SWCNT bundle interconnects exhibit higher transmission efficiency and lower reflection losses and less power dissipations. This is mainly due to larger conductivity of MWCNT and SWCNT bundle, proportional to the number of conducting shells (M) in MWCNT and conducting SWCNTs (N) in the bundle, respectively. With no special separation techniques, the metallic nanotubes are distributed with probability β = 1/3. While the proportion of metallic nanotubes can be potentially increased using techniques introduced by Peng et al. [193] and Zheng et al. [194], the delays in MWCNT and SWCNT bundle interconnects can be further decreased with increase in β and approaching to 1. It is also noticed that with the increase in interconnection length, the delay of Cu interconnect increases faster than that of MWCNT and SWCNT bundle interconnects. For applications requiring small circuit delays MWCNT interconnects should be used due to smaller capacitances. Applications requiring large transmission efficiency and low reflection losses, CNT bundles should be used for interconnects since the numbers of conducting channels per shell are more in SWCNTs bundle than the number of conducting channels per shell in MWCNT of the same size. These findings suggest that MWCNT and SWCNT bundle can replace Cu as interconnection wires in next generation of VLSI integrated circuits.

We have utilized our MWCNT and SWCNT bundle interconnects model in a widely used π model to study the performances of MWCNT and SWCNT bundle wire inductors and compared them with Cu inductors. The calculation results show that the Q factors of CNT wire (bundle and MWCNT) inductors are higher than that of the Cu wire inductor. This is mainly due to much lower resistance of CNT and negligible skin effect

higher oscillation frequency, lower phase noise, due to their smaller resistances and higher Q factors. It is also noticed that LC VCO using SWCNT bundle wire inductor has better performance when compared with the performance of LC VCO using MWCNT wire inductor due to its lower resistance and higher Q factor.

We have introduced several CMOS energy recovery circuits and focused on XNOR/XOR gates. We have also introduced a new improved clocked adiabatic logic (CAL) XNOR/XOR gates which consume significantly less power compared to earlier ERL implementations.

Using our CNT-FET models, we have extended the study of CMOS energy recovery logic to CNT-FET energy recovery logic. Our results show that the power density of CNT-FET circuits will exceed the maximum power density limit set by the ITRS 2003. Therefore, it is important to adopt circuit design techniques that would reduce on-chip power density for the future technology generations using CNT-FETs. Our simulations also show that energy recovery techniques help in reducing the power density of CNT-FET circuits below 1 GHz. Beyond 1 GHz, further work is needed to reduce the on-chip power density. Energy recovery is, thus, can be used as an alternative approach toward circuit designs for reduction of high power density.

Stuck-at fault, stuck-on fault and stuck-open fault models have been used in fault modeling behavior of CNT-FET NAND gate and simulated in Cadence/Spectre. Simulation results show that CNT-FET gates exhibits faulty behavior similar to traditional CMOS gates with stuck-at fault and stuck-on fault. CNT-FET gates also have some unique faults such as the metallic CNT faults, which result in CNT-FETs stuck-on and the output of the gate indeterminate.