In this thesis, existing approaches to bitstream relocation on FPGAs and their draw-backs have been discussed. This work proposes a novel multi-row M-FDR algorithm that can relocate frame data between PRRs faster than contemporary state-of-the-art relocation techniques by Corbetta et al. [4], Carver et al. [5], and Sudarsanam et al. [6]. The proposed algorithm has been implemented using a dedicated hardware architecture called the Accel-erated Memory-based Reconfiguration Circuit (AMRC). A performance estimation model of the AMRC has been proposed that quantifies the performance benefit of AMRC over ARC [6], which was found to be the fastest relocation method among previous approaches that were studied. AMRC was found to be on an average 26.6% faster than ARC [6] when relocating PRRs. An average speedup of 231x over BiRF [4], while for the method proposed by Carver et al. [5] a speedup of 9.2x for circuits on the same side of the FPGA, and 24.2x for circuits on the opposite side of the FPGA was observed.
The major challenge in this thesis involved understanding the existing relocation tech-niques like PRR-PRR relocation [6] and BiRF [4] and identifying their drawbacks. Several tests were used to help identify the performance bottlenecks when using the ICAP and off-chip versus on-off-chip memory during frame data relocation. Another important constraint to manage during M-FDR is that the ICAP cannot be written more than 2048 frame data words at once. Therefore for larger designs, a column pattern had to be identified for copy-ing frames in groups of either two CLB columns, or one CLB and one DSP column, or one BRAM column, because of the way columns are addressed and arranged in Xilinx Virtex-4 FPGAs. Bit reversal is an important consideration when moving frames to the opposite side of the FPGA. The AMRC has been designed to handle configuration requests to any side of the FPGA and to reverse bits for only those frames that fall on the opposite side of
Future research can be carried out in the following directions.
1. Use compression techniques to reduce the memory footprint of frame data in the FDB for efficient on-chip memory utilization.
2. Implement the AMRC on FPGAs with higher gate densities like the Virtex-5 and Virtex-6 families of Xilinx FPGAs to reduce the penalty of using on-chip memory to store frame data.
3. Improve the AMRC hardware to store more than one circuit in the FDB, so as to support a more granular form of run-time parallelization between PRMs.
4. Implement sharing of the FDB between the static and reconfigurable regions of the SoC so that unused BRAM memory in the FDB can be re-used by the static region for storage.
5. Investigate ways to further improve the relocation time, such as reducing relocation overhead during the frame read process, and implementing bulk frame reads.
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