The NoC interconnect is critical to the lifetime survival of the CMP system. In this work, we extended the novel wearout-decelerating scheme proposed by H.Kim et al. [25] in which routers under low load have their wearout-sensitive components exer-cised, without significantly impacting cycle time, pipeline depth, power consumption or area of the overall router. The exercise mode data is generated deterministi-cally for maximum impact. We subsequently show that the proposed design yields a
∼2300× increase in router lifetime because of reduced NBTI wearout. In this work we have used a simple ATPG algorithm to generate the exercise mode data. It might be further possible to use advanced ATPG techniques which can result in reduction of ROM size needed to store the exercise mode data. This technique of using ATPG techniques to generate appropriate exercise mode data can be used for any arbitrary circuits. The ideal case would be when this technique can be incorporated as an additional option in the synthesis step of ASIC design flow. Then the tool chain can automatically determine the aging sensitive paths and will be able to generate additional logic required for the mitigation of such degradation.
REFERENCES
[1] Jaume Abella, Xavier Vera, and Antonio Gonzalez. Penelope: The nbti-aware processor. In Proceedings of the 40th Annual IEEE/ACM International Sympo-sium on Microarchitecture (MICRO), pages 85–96. IEEE, 2007.
[2] Miron Abramovici, Melvin A Breuer, and Arthur D Friedman. Digital systems testing and testable design. Wiley-IEEE Press, Hoboken, New Jersey, USA, 1994.
[3] JEDEC Solid State Technology Association. Failure Mechanisms and Models for Semiconductor Devices, JEP122G, http://www.jedec.org/sites/ default/files/-docs/JEP122G.pdf. Technical report, October 2011.
[4] Daniel U Becker. Efficient Microarchitecture for Network-on-Chip Routers. PhD thesis, Stanford University, Stanford, CA, USA., 2012.
[5] Kshitij Bhardwaj, Koushik Chakraborty, and Sanghamitra Roy. An milp-based aging-aware routing algorithm for nocs. In Proceedings of the Conference on Design, Automation and Test in Europe, pages 326–331. EDA Consortium, 2012.
[6] Kshitij Bhardwaj, Koushik Chakraborty, and Sanghamitra Roy. Towards grace-ful aging degradation in nocs through an adaptive routing algorithm. In Pro-ceedings of the 49th Design Automation Conference (DAC), pages 382–391.
ACM/EDAC/IEEE, 2012.
[7] Christian Bienia, Sanjeev Kumar, Jaswinder Pal Singh, and Kai Li. The PAR-SEC benchmark suite: Characterization and architectural implications. In
Pro-ceedings of the 17th international conference on Parallel architectures and com-pilation techniques, pages 72–81. ACM, 2008.
[8] David R Bild, Robert P Dick, and Gregory E Bok. Static nbti reduction using internal node control. ACM Transactions on Design Automation of Electronic Systems (TODAES), 17(4):45:1–45:30, 2012.
[9] Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R Hower, Tushar Krishna, Somayeh Sardashti, et al. The gem5 simulator. ACM SIGARCH Computer Architecture News, 39(2):1–7, 2011.
[10] Jason Blome, Shuguang Feng, Shantanu Gupta, and Scott Mahlke. Self-calibrating online wearout detection. In Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, pages 109–122.
IEEE Computer Society, 2007.
[11] Michael Bushnell and Vishwani D Agrawal. Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits, volume 17. Springer Science &
Business Media, New York, USA, 2000.
[12] William J Dally and Brian Towles. Route packets, not wires: On-chip intercon-nection networks. In Proceedings of the Design Automation Conference, pages 684–689. IEEE, 2001.
[13] Andrew DeOrio, Kostantinos Aisopos, Valeria Bertacco, and Li-Shiuan Peh.
DRAIN: Distributed recovery architecture for inaccessible nodes in multi-core chips. In Proceedings of the 48th Design Automation Conference, pages 912–917.
ACM, 2011.
[14] Jianxin Fang and Sachin S Sapatnekar. Incorporating hot-carrier injection ef-fects into timing analysis for large circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(12):2738–2751, 2014.
[15] David Fick, Andrew DeOrio, Gregory Chen, Valeria Bertacco, Dennis Sylvester, and David Blaauw. A highly resilient routing algorithm for fault-tolerant nocs.
In Proceedings of the Conference on Design, Automation and Test in Europe, pages 21–26. European Design and Automation Association, 2009.
[16] International Technology Roadmap for Semiconductors (ITRS). Process integration, devices, and structures (PIDS), http://www.itrs.net/itrs%201999-2014%20mtgs,%20presentations%20&%20links/2009itrs/2009chapters
2009tables/2009 pids.pdf. Technical report, 2009.
[17] Xin Fu, Tao Li, and Jos´e AB Fortes. Architecting reliable multi-core network-on-chip for small scale processing technology. In Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), pages 111–120. IEEE, 2010.
[18] Prabhakar Goel. An implicit enumeration algorithm to generate tests for com-binational logic circuits. IEEE Transactions on Computers, 100(3):215–222, 1981.
[19] Erika Gunadi, Abhisek A Sinkar, Nam Sung Kim, and Mikko H Lipasti. Com-bating aging with the colt duty cycle equalizer. In Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, pages 103–114. IEEE Computer Society, 2010.
[20] Xinfei Guo, Wayne Burleson, and Mircea Stan. Modeling and experimental demonstration of accelerated self-healing techniques. In Proceedings of the 51st Annual Design Automation Conference, pages 1–6. ACM, 2014.
[21] Saket Gupta and Sachin S Sapatnekar. Employing circadian rhythms to enhance power and reliability. ACM Transactions on Design Automation of Electronic Systems (TODAES), 18(3):38:1–38:23, 2013.
[22] Jason Howard, Saurabh Dighe, Sriram R Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries, et al. A 48-core ia-32 processor in 45 nm cmos using on-die message-passing and dvfs for performance and power scaling. Journal of Solid-State Circuits, 46(1):173–183, 2011.
[23] Lin Huang and Qiang Xu. Agesim: a simulation framework for evaluating the lifetime reliability of processor-based socs. In Proceedings of the Conference on Design, Automation and Test in Europe, pages 51–56. ACM, 2010.
[24] Ulya R Karpuzcu, Brian Greskamp, and Josep Torrellas. The BubbleWrap many-core: popping cores for sequential acceleration. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 447–458. IEEE, 2009.
[25] Hyungjun Kim, Arseniy Vitkovskiy, Paul V Gratz, and Vassos Soteriou. Use it or lose it: wear-out and lifetime in future chip multiprocessors. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, pages 136–147. ACM, 2013.
[26] Veit B Kleeberger, Martin Barke, Christoph Werner, Doris Schmitt-Landsiedel, and Ulf Schlichtmann. A compact model for nbti degradation and recovery under
use-profile variations and its application to aging analysis of digital integrated circuits. Microelectronics Reliability, 54(6):1083–1089, 2014.
[27] Sanjay V Kumar, Chris H Kim, and Sachin S Sapatnekar. Impact of nbti on sram read stability and design for reliability. In Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED), pages 210–218. IEEE, 2006.
[28] Liangzhen Lai, Vishal Chandra, Robert Aitken, and Puneet Gupta. BTI-Gater:
An Aging-Resilient Clock Gating Methodology. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 4(2):180–189, 2014.
[29] Xiaojun Li, Jin Qin, and Joseph B Bernstein. Compact modeling of mosfet wearout mechanisms for circuit-reliability simulation. IEEE Transactions on Device and Materials Reliability, 8(1):98–121, 2008.
[30] Yanjing Li, Samy Makar, and Subhasish Mitra. CASP: concurrent autonomous chip self-test using stored test patterns. In Proceedings of the conference on Design, automation and test in Europe, pages 885–890. ACM, 2008.
[31] Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan Yang, and Xuan Zeng.
Statistical reliability analysis under process variation and aging effects. In Pro-ceedings of the 46th Annual Design Automation Conference, pages 514–519.
ACM, 2009.
[32] Elie Maricau and Georges Gielen. A methodology for measuring transistor age-ing effects towards accurate reliability simulation. In Proceedage-ings of the 15th IEEE International On-Line Testing Symposium (IOLTS), pages 21–26. IEEE, 2009.
[33] Stelios N Neophytou and Maria K Michael. Test set generation with a large number of unspecified bits using static and dynamic techniques. IEEE Trans-actions on Computers, 59(3):301–316, 2010.
[34] Fabian Oboril and Mehdi Tahoori. Arise: Aging-aware instruction set encoding for lifetime improvement. In Proceedings of the 19th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 207–212. IEEE, 2014.
[35] Fabian Oboril and Mehdi B Tahoori. ExtraTime: Modeling and analysis of wearout due to transistor aging at microarchitecture-level. In Proceedings of the 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), pages 1–12. IEEE, 2012.
[36] Fabian Oboril and Mehdi B Tahoori. Aging-aware design of microprocessor in-struction pipelines. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33(5):704–716, 2014.
[37] Li-Shiuan Peh and William J Dally. A delay model and speculative architecture for pipelined routers. In Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA), pages 255–266. IEEE, 2001.
[38] Michael D Powell, Arijit Biswas, Shantanu Gupta, and Shubhendu S Mukherjee.
Architectural core salvaging in a multi-core processor for hard-error tolerance.
ACM SIGARCH Computer Architecture News, 37(3):93–104, 2009.
[39] Kewal K Saluja, Shriram Vijayakumar, Warin Sootkaneung, and Xaingning Yang. NBTI degradation: A problem or a scare? In Proceedings of the 21st International Conference on VLSI Design (VLSID), pages 137–142. IEEE, 2008.
[40] Timo Schonwald, Jochen Zimmermann, Oliver Bringmann, and Wolfgang Rosenstiel. Fully adaptive fault-tolerant routing algorithm for network-on-chip architectures. In Proceedings of the 10th Euromicro Conference on Digital Sys-tem Design Architectures, Methods and Tools (DSD), pages 527–534. IEEE, 2007.
[41] Jared C Smolens, Brian T Gold, James C Hoe, Babak Falsafi, and Ken Mai.
Detecting emerging wearout faults. In Proceedings of the 3rd Workshop on Silicon Errors in Logic-System Effects, pages 23–29. IEEE, 2007.
[42] Bogdan Tudor, Joddy Wang, Zhaoping Chen, Robin Tan, Weidong Liu, and Frank Lee. An accurate and scalable mosfet aging model for circuit simula-tion. In Proceedings of the 12th International Symposium on Quality Electronic Design (ISQED), pages 1–4. IEEE, 2011.
[43] Yao Wang, Sorin Cotofana, and Liang Fang. A unified aging model of nbti and hci degradation towards lifetime reliability management for nanoscale mosfet circuits. In Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, pages 175–180. IEEE Computer Society, 2011.
[44] Zhen Zhang, Alain Greiner, and Sami Taktak. A reconfigurable routing algo-rithm for a fault-tolerant 2d-mesh network-on-chip. In Proceedings of the 45th ACM/IEEE Design Automation Conference (DAC), pages 441–446. IEEE, 2008.