This section provides brief descriptions and pin-out definitions for onboard headers and connectors. Be sure to use the correct cable for each header or connector.
A. 24-Pin ATX Main PWR B. 8-Pin Processor PWR
B A
ATX Power 24-pin Connector Pin Definitions (JPW1) Pin# Definition Pin # Definition 12V 8-pin Power
Connec-tor Pin Definitions Pins Definition 1 through 4 Ground 5 through 8 +12V
ATX Main PWR (JPW1) & CPU PWR Connectors (JPW2)
The 24-pin main power connector (JPW1) is used to provide power to the motherboard. The 8-pin CPU PWR connector (JPW2) is also required for the processor. These power connectors meet the SSI EPS 12V specification. See the table on the right for pin definitions.
8-Pin Processor PWR
A B
24-Pin Main PWR
JLAN1JLAN2
14JUIDB1 JSTBY1
1 3
JIPMB1 JI2C1
1 5 Socket R LGA 2011 CPU
DESIGNED IN USA
SXB2
T-SGPIO187 21
JPG1 JPB1 JP3
JPME1
JWD
JPL1
1 3
SXB1B: LEFT_WIO_MIDDLESXB2: RIGHT_WIO
SXB1A: LEFT_WIO_UP
WRITE PROTECTJWP1: USBUSB
1-2:RST 2-3:NIMI
JWD:
JI2C2/JI2C3 1-2:Enable 2-3:Disabl
e JPMB OFF:NORMALON:ME RECOVERYJPME1:
VGAUID JSTBY1:STAND BY POWER FOR DOM
2-3:NMI1-2:RST(DE
FAULT)JWD:WATCH DOG TIMER JD1:4-7:SPEAKER1-2:PWR_LED
IPMI LAN USB/0/1
1-2:ENABLE 2-3:DISABL
E
JPL2:LAN2
JPL1:LAN12-3:DISABLE1-2:ENABLE JPB1: BMC
COM1
2-3:Disable1-2:Enable JOH1:OVER HEAT LED CPU
OFF:DisableON:Enable
CLOSE 1st OPEN 1st
JI2C2 JI2C3
LED2
Fan Header Pin Definitions Pin# Definition 1 Ground (Black) 2 +12V (Red) 3 Tachometer 4 PWM_Control
Fan Headers (FAN1~5)
The X9SRW series has five fan headers (Fan 1~Fan 5). These fans are 4-pin fan headers.
Pins 1-3 of the fan headers are backward com-patible with the traditional 3-pin fans, but will only run at full speed. To take advantage of the fan speed control setting in the BIOS Hard-ware Monitoring section, please use 4-pin fans.
This will allow the BIOS to automatically set fan speeds based on the system temperature.
Refer to the table on the right for pin definitions.
A
G. Chassis Intrusion
C D Chassis Intrusion (JL1)
A Chassis Intrusion header is located at JL1 on the motherboard. Attach the appropriate cable from the chassis to inform you of a chassis intru-sion when the chassis is opened.
Chassis Intrusion Pin Definitions (JL1) Pin# Definition 1 Intrusion Input
2 Ground
G
E
JLAN1JLAN2
DESIGNED IN USA
SXB2
T-SGPIO187 21
SXB1A SAS2SAS1
SAS3SAS4
JPG1 JPB1 JP3
JPME1
JWD
JPL1
1 3
SXB1B: LEFT_WIO_MIDDLESXB2: RIGHT_WIO
SXB1A: LEFT_WIO_UP
WRITE PROTECTJWP1: USBUSB
1-2:RST 2-3:NIMI
JWD:
JI2C2/JI2C3 1-2:Enable 2-3:Disabl
e JPMB OFF:NORMALON:ME RECOVERYJPME1:
VGAUID JSTBY1:STAND BY POWER FOR DOM
2-3:NMI1-2:RST(DE
FAULT)JWD:WATCH DOG TIMER JD1:4-7:SPEAKER1-2:PWR_LED
IPMI LAN USB/0/1
1-2:ENABLE 2-3:DISABL
E
JPL2:LAN2
JPL1:LAN12-3:DISABLE1-2:ENABLE JPB1: BMC
COM1
2-3:Disable1-2:Enable JOH1:OVER HEAT LED CPU
OFF:DisableON:Enable
CLOSE 1st OPEN 1st
JI2C2 JI2C3
LED2
A. Internal Speaker B. Wake On LAN Speaker (JD1)
On the JD1 header, pins 3~4 are used for the internal speaker. Close pins 3~4 with a jumper or cap to use the onboard speaker.
If you wish to use an external speaker, at-tach the external speaker's cable to pins Pins 3~4 Internal Speaker Pins1~4 External Speaker
B A
Legacy Wake-On-LAN Header (JSTBY) The onboard LANs (LAN1 and LAN2) do not need a WOL header to support its Wake-On-LAN function. We preserved the legacy WOL header to provide con-venience for some embedded customers who need internal power source from the board. See the table on the right for pin definitions.
Wake-On-LAN Pin Definitions Pin# Definition 1 +5V Standby
2 Ground
3 Wake-up
JLAN1JLAN2
DESIGNED IN USA
SXB2
T-SGPIO187 21
SXB1A SAS2SAS1
SAS3SAS4
JPG1 JPB1 JP3
JPME1
JWD
JPL1
1 3
SXB1B: LEFT_WIO_MIDDLESXB2: RIGHT_WIO
SXB1A: LEFT_WIO_UP
WRITE PROTECTJWP1: USBUSB
1-2:RST 2-3:NIMI
JWD:
JI2C2/JI2C3 1-2:Enable 2-3:Disabl
e JPMB OFF:NORMALON:ME RECOVERYJPME1:
VGAUID JSTBY1:STAND BY POWER FOR DOM
2-3:NMI1-2:RST(DE
FAULT)JWD:WATCH DOG TIMER JD1:4-7:SPEAKER1-2:PWR_LED
IPMI LAN USB/0/1
1-2:ENABLE 2-3:DISABL
E
JPL2:LAN2
JPL1:LAN12-3:DISABLE1-2:ENABLE JPB1: BMC
COM1
2-3:Disable1-2:Enable JOH1:OVER HEAT LED CPU
OFF:DisableON:Enable
CLOSE 1st OPEN 1st
JI2C2 JI2C3
LED2
A. Power Supply I2C B. DOM Power Power Supply I2C (JPI2C)
The Power Supply I2C Connector, located at JPI2C, monitors the status of the power supply, fan and system temperature. See the table on the right for pin definitions.
PWR Supply I2C Pin Definitions Pin# Definition DOM PWR Connector (JSD1)
The Disk-On-Module (DOM) power connector, located at JSD1, provides 5V (Gen1/Gen) power to a solid-state DOM storage device connected to one of the SATA ports. See the table on the right for pin definitions.
DOM PWR Pin Definitions Pin# Definition
1 5V
2 Ground
3 Ground
JLAN1JLAN2
DESIGNED IN USA
SXB2
T-SGPIO187 21
JPG1 JPB1 JP3
JPME1
JWD
JPL1
1 3
WRITE PROTECTJWP1: USBUSB
1-2:RST 2-3:NIMI
JWD:
JI2C2/JI2C3 1-2:Enable 2-3:Disabl
e JPMB OFF:NORMALON:ME RECOVERYJPME1:
VGAUID JSTBY1:STAND BY POWER FOR DOM
2-3:NMI1-2:RST(DEFAULT)JWD:WATCH DOG TIMER JD1:4-7:SPEAKER1-2:PWR_LED
IPMI LAN USB/0/1
1-2:ENABLE 2-3:DISABL
E
JPL2:LAN2
JPL1:LAN12-3:DISABLE1-2:ENABLE JPB1: BMC
COM1
2-3:Disable1-2:Enable JOH1:OVER HEAT LED CPU
OFF:DisableON:Enable
CLOSE 1st OPEN 1st
JI2C2 JI2C3
LED2
C
Serial_Link-SGPIO Pin Definitions Pin# Definition Pin Definition
1 NC 2 NC
3 Ground 4 DATA Out
5 Load 6 Ground
7 Clock 8 NC
NC: No Connections
A. T-SGPIO 1 B. T-SGPIO 2 C. T-SGPIO 3 A
B T-SGPIO 1/2 & 3-SGPIO 1/2 Headers Two T-SGPIO (Serial-Link General Pur-pose Input/Output) headers are located next to the I-SATA Ports on the mother-board. Additionally, two 3-SGPIO ports (for SAS) are also located next to USB 8/9 . These headers are used to com-municate with the enclosure manage-ment chip in the system. See the table on the right for pin definitions. Refer to the board layout below for the locations of the headers.
Trusted Platform Module Header Pin Definitions Pin # Definition Pin # Definition
1 LCLK 2 GND
3 LFRAME 4 No Pin
5 LRESET 6 VCC5
7 LAD3 8 LAD2
9 VCC3 10 LAD1
11 LAD0 12 GND
13 RSV0 14 RSV1
15 SB3V 16 SERIRQ
17 GND 18 CLKRUN
19 LPCPD 20 RSV2
TPM Header (JTPM1)
This header is used to connect a Trusted Platform Module (TPM), which is available from a third-party vendor.
A TPM is a security device that sup-ports encryption and authentication in hard drives. It enables the moth-erboard to deny access if the TPM associated with the hard drive is not installed in the system. See the table on the right for pin definitions.
D
E
D. T-SGPIO 4 E. TPM Header
JLAN1JLAN2
DESIGNED IN USA
SXB2
T-SGPIO187 21
SXB1A SAS2SAS1
SAS3SAS4
JPG1 JPB1 JP3
JPME1
JWD
JPL1
1 3
SXB1B: LEFT_WIO_MIDDLESXB2: RIGHT_WIO
SXB1A: LEFT_WIO_UP
WRITE PROTECTJWP1: USB
USB
1-2:RST 2-3:NIMI
JWD:
JI2C2/JI2C3 1-2:Enable 2-3:Disabl
e JPMB OFF:NORMALON:ME RECOVERYJPME1:
VGAUID JSTBY1:STAND BY POWER FOR DOM
2-3:NMI1-2:RST(DEFAULT)JWD:WATCH DOG TIMER JD1:4-7:SPEAKER1-2:PWR_LED
IPMI LAN USB/0/1
1-2:ENABLE 2-3:DISABL
E
JPL2:LAN2
JPL1:LAN12-3:DISABLE1-2:ENABLE JPB1: BMC
COM1
2-3:Disable1-2:Enable JOH1:OVER HEAT LED CPU
OFF:DisableON:Enable
CLOSE 1st OPEN 1st
JI2C2 JI2C3
LED2
A. Overheat/Fan Fail LED
A
Overheat/Fan Fail LED (JOH1)
The JOH1 header is used to connect an LED to provide warnings of chassis over-heat. This LED will also blink to indicate a fan failure. Refer to the table on right for pin definitions.
Overheat LED Pin Definitions Pin# Definition
1 5vDC
2 OH Active
OH/Fan Fail LED Pin Definitions State Message Solid Overheat Blinking Fan Fail