➁ Stop Timer Operation
Timer 1 is temporarily stopped. [TW1A]
Timer 1 count source is selected. b3: Timer 1 count auto-stop circuit not selected
b3 b0 b2: Timer 1 stop
Timer control register W1 0 0 0 0 b1, b0: Instruction clock (INSTCK) selected for Timer 1 count source
↓↓↓↓↓
➂ Set Timer Value
Timer 1 count time is set. (The formula is shown *A below.)
Timer 1 reload register R1 “A616” Timer count value 166 set [T1AB]
↓↓↓↓↓
➃ Clear Interrupt Request
Timer 1 interrupt activated condition is cleared.
Timer 1 interrupt request flag T1F 0 Timer 1 interrupt activated condition cleared [SNZT1]
↓↓↓↓↓
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the interrupt request flag T1F,
insert the NOP instruction after the SNZT1 instruction.
↓↓↓↓↓
➄ Start Timer Operation
Timer 1 temporarily stopped is restarted.
b3 b0
Timer control register W1 0 1 0 0 b2: Timer 1 operation start [TW1A]
↓↓↓↓↓
➅ Enable Interrupts
The Timer 1 interrupt which is temporarily disabled is enabled.
b3 b0
Interrupt control register V1 ✕ 1 ✕ ✕ b2: Timer 1 interrupt occurrence enabled [TV1A]
Interrupt enable flag INTE 1 All interrupts enabled [EI]
↓↓↓↓↓
Constant period interrupt execution started
*A: The timer 1 count value to make the interrupt occur every 0.25 ms is set as follows.
0.25 ms ≅ (2.0 MHz)-1 ✕ 3 ✕ (166+1)
“✕”: it can be “0” or “1.”
“[ ]”: instruction
( )
System clock Instruction clock
Timer 1 count value
Fig. 2.2.6 Timer 2 constant period interrupt setting example
➀ Disable Interrupts
Timer 2 interrupt is temporarily disabled.
Interrupt enable flag INTE 0 All interrupts disabled [DI]
b3 b0
Interrupt control register V1 0 ✕ ✕ ✕ b3: Timer 2 interrupt occurrence disabled [TV1A]
↓↓↓↓↓
➁ Stop Timer and Prescaler Operation
Timer 2 and prescaler are temporarily stopped.
Timer 2 count source is selected. [TW2A]
b3 b0 b2: Timer 2 stop
Timer control register W2 ✕ 0 0 1 b1, b0: Prescaler output (ORCLK) selected for
b0 Timer 2 count source Timer control register PA 0 Prescaler stop [TPAA]
↓↓↓↓↓
➂ Set Timer Value and Prescaler Value
Timer 2 and prescaler count times are set. (The formula is shown *A below.)
Timer 2 reload register R2 “5216” Timer count value 82 set [T2AB]
Prescaler reload register RPS “0F16” Prescaler count value 15 set [TPSAB]
↓↓↓↓↓
➃ Clear Interrupt Request
Timer 2 interrupt activated condition is cleared.
Timer 2 interrupt request flag T2F 0 Timer 2 interrupt activated condition cleared [SNZT2]
↓↓↓↓↓
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the interrupt request flag T2F,
insert the NOP instruction after the SNZT2 instruction.
↓↓↓↓↓
➄ Start Timer Operation and Prescaler Operation
Timer 2 and prescaler temporarily stopped are restarted.
b3 b0
Timer control register W2 ✕ 1 0 1 b2: Timer 2 operation start [TW2A]
b0
Timer control register PA 1 Prescaler start [TPAA]
↓↓↓↓↓
➅ Enable Interrupts
The Timer 2 interrupt which is temporarily disabled is enabled.
b3 b0
Interrupt control register V1 1 ✕ ✕ ✕ b3: Timer 2 interrupt occurrence enabled [TV1A]
Interrupt enable flag INTE 1 All interrupts enabled [EI]
↓↓↓↓↓
Constant period interrupt execution started
*A: The prescaler count value and timer 2 count value to make the interrupt occur every 1 ms are set as follows.
1 ms ≅ (4.0 MHz)-1 ✕ 3 ✕ (15 +1) ✕ (82 +1)
“✕”: it can be “0” or “1.”
“[ ]”: instruction
( )
System clock Instruction clock
Timer 2 count value Prescaler
count value
➀ Disable Interrupts
Timer 3 interrupt is temporarily disabled.
Interrupt enable flag INTE 0 All interrupts disabled [DI]
b3 b0
Interrupt control register V2 ✕ ✕ ✕ 0 b0: Timer 3 interrupt occurrence disabled [TV2A]
↓↓↓↓↓
➁ Stop Timer Operation
Timer 3 and prescaler are temporarily stopped.
Timer 3 count source is selected. [TW3A]
b3 b0 b3: Timer 3 count auto-stop circuit not selected Timer control register W3 0 0 0 1 b2: Timer 3 stop
b1, b0: Prescaler output (ORCLK) selected for
b0 Timer 3 count source Timer control register PA 0 Prescaler stop [TPAA]
↓↓↓↓↓
➂ Set Timer Value and Prescaler Value
Timer 3 and prescaler count times are set. (The formula is shown *A below.)
Timer 3 reload register R3 “5216” Timer count value 82 set [T3AB]
Prescaler reload register RPS “0F16” Prescaler count value 15 set [TPSAB]
↓↓↓↓↓
➃ Clear Interrupt Request
Timer 3 interrupt activated condition is cleared.
Timer 3 interrupt request flag T3F 0 Timer 3 interrupt activated condition cleared [SNZT3]
↓↓↓↓↓
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the interrupt request flag T3F,
insert the NOP instruction after the SNZT3 instruction.
↓↓↓↓↓
➄ Start Timer Operation and Prescaler Operation
Timer 3 and prescaler temporarily stopped are restarted.
b3 b0
Timer control register W3 0 1 0 1 b2: Timer 3 operation start [TW3A]
b0
Timer control register PA 1 Prescaler start [TPAA]
↓↓↓↓↓
➅ Enable Interrupts
The Timer 3 interrupt which is temporarily disabled is enabled.
b3 b0
Interrupt control register V2 ✕ ✕ ✕ 1 b0: Timer 3 interrupt occurrence enabled [TV2A]
Interrupt enable flag INTE 1 All interrupts enabled [EI]
↓↓↓↓↓
Constant period interrupt execution started
*A: The prescaler count value and timer 3 count value to make the interrupt occur every 1 ms are set as follows.
1 ms ≅ (4.0 MHz)-1 ✕ 3 ✕ (15 +1) ✕ (82 +1)
( )
System clock Instruction clock
Timer 3 count value Prescaler
count value
Fig. 2.2.8 Timer 4 constant period interrupt setting example
Timer 4 and serial I/O interrupts are temporarily disabled.
Interrupt enable flag INTE 0 All interrupts disabled [DI]
b3 b0
Interrupt control register V2 0 ✕ ✕ ✕ b3: Timer 4 and serial I/O interrupts occurrence disabled [TV2A]
↓↓↓↓↓
➁ Stop Timer and Prescaler Operation [TW4A]
Timer 4 and prescaler are temporarily stopped. b3: CNTR1 output invalid
Timer 4 count source is selected. b2: PWM signal “H” interval expansion function invalid
b3 b0 b1: Timer 4 stop
Timer control register W4 0 0 0 1 b0: Prescaler output (ORCLK) divided by 2 selected
b0 for Timer 4 count source Timer control register PA 0 Prescaler stop [TPAA]
↓↓↓↓↓
➂ Select Timer 4 Interrupt
Timer 4 is selected for the interrupt source.
b0
Interrupt control register I3 0 Timer 4 interrupt valid [TI3A]
↓↓↓↓↓
➃ Set Timer Value and Prescaler Value
Timer 4 and prescaler count times are set. (The formula is shown *A below.)
Timer 4 reload register R4L “DD16” Timer count value 221 set [T4AB]
Prescaler reload register RPS “9516” Prescaler count value 149 set [TPSAB]
↓↓↓↓↓
➄ Clear Interrupt Request
Timer 4 interrupt activated condition is cleared.
Timer 4 interrupt request flag T4F 0 Timer 4 interrupt activated condition cleared [SNZT4]
↓↓↓↓↓
Note when the interrupt request is cleared
When ➄ is executed, considering the skip of the next instruction according to the interrupt request flag T4F,
insert the NOP instruction after the SNZT4 instruction.
↓↓↓↓↓
➅ Start Timer Operation and Prescaler Operation
Timer 4 and prescaler temporarily stopped are restarted.
b3 b0
Timer control register W4 0 0 1 1 b1: Timer 4 operation start [TW4A]
b0
Timer control register PA 1 Prescaler start [TPAA]
↓↓↓↓↓
➆ Enable Interrupts
The Timer 4 interrupt which is temporarily disabled is enabled.
b3 b0
Interrupt control register V2 1 ✕ ✕ ✕ b3: Timer 4 interrupt occurrence enabled [TV2A]
Interrupt enable flag INTE 1 All interrupts enabled [EI]
↓↓↓↓↓
Constant period interrupt execution started
*A: The prescaler count value and timer 4 count value to make the interrupt occur every 50 ms are set as follows.
50 ms ≅ (4.0 MHz)-1 ✕ 3 ✕ (149 +1) ✕ 2 ✕ (221 +1)
“✕”: it can be “0” or “1.”
“[ ]”: instruction
( )
System clock Instruction clock
Timer 4 count value Prescaler
count value Timer 4 count source
Fig. 2.2.9 Timer 5 constant period interrupt setting example
➀ Disable Interrupts
Timer 5 interrupt is temporarily disabled.
Interrupt enable flag INTE 0 All interrupts disabled [DI]
b3 b0
Interrupt control register V2 ✕ ✕ 0 ✕ b1: Timer 5 interrupt occurrence disabled [TV2A]
↓↓↓↓↓
➁ Set Timer Value
Timer 5 is temporarily stopped.
Timer 5 count time is set. [TW5A]
(The formula is shown *A below.) b3 b0 b2: Timer 5 stop
Timer control register W5 ✕ 0 0 1 Timer 5 count value initialized b1,b0: Timer count value 214 set
↓↓↓↓↓
➂ Clear Interrupt Request
Timer 5 interrupt activated condition is cleared.
Timer 5 interrupt request flag T5F 0 Timer 5 interrupt activated condition cleared [SNZT5]
↓↓↓↓↓
Note when the interrupt request is cleared
When ➂ is executed, considering the skip of the next instruction according to the interrupt request flag T5F,
insert the NOP instruction after the SNZT5 instruction.
↓↓↓↓↓
➃ Start Timer Operation
Timer 5 temporarily stopped is restarted.
b3 b0
Timer control register W5 ✕ 1 0 1 b2: Timer 5 operation start [TW5A]
↓↓↓↓↓
➄ Enable Interrupts
The Timer 5 interrupt which is temporarily disabled is enabled.
b3 b0
Interrupt control register V2 ✕ ✕ 1 ✕ b1: Timer 5 interrupt occurrence enabled [TV2A]
Interrupt enable flag INTE 1 All interrupts enabled [EI]
↓↓↓↓↓
Constant period interrupt execution started
*A: The timer 5 count value to make the interrupt occur every 500 ms is set as follows.
500 ms = (32.768 kHz)–1 ✕ 214
“✕”: it can be “0” or “1.”
“[ ]”: instruction
( )
Sub-clock Timer 5 count value