Device Control Register Functions
The Control register supports several functions defined below. Figure 12-2 on page 223 illustrates the Control register bit field designations.
• nIEN (Interrupt Enable, negative logic) when nIEN is cleared (0), interrupt request generation is enabled within the device, while setting the bit dis- ables interrupt generation.
• SRST (Soft Reset) — Software sets this bit to reset the drive. Reset is asserted when the SRST bit is set (1) and is cleared when the SRST bit is cleared (0). • HOB (High Order Byte) — Some register address support back-to-back
byte-sized writes to the same address location to load additional values to support features such as 48-bit Logical Block Addressing. Setting the HOB bit enables software to read the previous written byte from the selected 8-bit register.
Interrupt Enable (nIEN) Control Protocol
The nIEN bit is implemented to provide legacy software support. Following reset the nIEN bit is cleared, resulting in interrupts being enabled. Software can disable interrupts by setting the nIEN bit. When software either sets or clears the nIEN bit, a Register FIS is delivered to the SATA drive; thereby, setting or clearing the nIEN bit within the drive’s control register. Note, that any write to the shadow control register clears an interrupt pending condition within the HBA.
Also, unlike the PATA environment, the nIEN bit has no affect on a SATA drive’s behavior. In the SATA environment the HBA actually signals interrupt requests and also handles the nIEN function.
SATA Storage Technology
Software Reset (SRST)
Software resets a SATA drive in legacy fashion by writing a one to the SRST bit within the shadow Control register. This of course causes the HBA to send a Register FIS (with “C” bit cleared) to the drive. Software must write a zero to the SRST bit to clear the reset.
An SRST affects only the SATA device and has no effect on the link (unlike a COMRESET). Also during a soft reset the SATA device performs internal diag- nostics and once the SRST bit is cleared (followed be a Host-to-Device Register FIS) the drive returns a Register FIS to the HBA to report results of the drive’s diagnostics. This SATA drive protocol is illustrated in Figure 12-4 and described below:
1. The HBA has delivered a Register FIS to the drive to notify it that software has set the SRST bit in the shadow Command register. The Device is cur- rently sending logical idle when the drive receives the Register FIS.
2. The drive checks the FIS type and detects the C bit cleared and the SRST bit set; thereby, indicating that Software has issued a Reset.
3. During the Reset_Assert state, the drive re-initializes to its default state, starts internal diagnostics, and waits for software to clear the reset condi- tion.
4. The drive receives the second Register FIS with the C bit clear and SRST bit cleared, causing transition to the Execute Diagnostic state. The drive waits for the diagnostics to complete (if not already done) and updates its ATA registers to report either good or bad status.
5. The drive sends a Register FIS to the HBA to report the results.
Figure 12-3 illustrates the contents of the ATA registers when reporting both good and bad status. When bad status is returned, the Error register contains a drive-specific error code (any value except 01h).
Chapter 12: Control Protocol
Figure 12-3: Soft Reset Status Values
13
SATA II Features
Previous Chapter
The previous chapter discussed the functions associated with the Device Con- trol register. Writing to the Device Control register forces the HBA to send a Register FIS to the device. The particular bits written force the drive to take the specified action. Each of the Control register functions is discussed in detail.
This Chapter
This chapter introduces the primary features added by the SATA II specification and describes the motivation for adding them.
The Next Chapter
The next chapter describes the concepts and mechanisms associated with Native Command Queuing (NCQ). This mechanism provides major perfor- mance improvements over mainstream ATA and SATA drives that use standard DMA Read and Write operations.
Overview
The SATA II implementation was introduced as an extension to the initial SATA specification. SATA II introduced many new features most of which are optional. The new features fall into several categories:
• Performance and Reliability Features — Higher transmission rates and sup- port for Native Command Queuing are among the most important improvements added by SATA II.
• Server-specific Support — Many new SATA II features focused on making SATA more appealing for server applications. Most of the server-related enhancements focus more on the SATA infrastructure and less on the drives themselves.
• Fixes and Enhancements to SATA — A variety of fixes and miscellaneous features were added to SATA II; including, asynchronous event notification.
SATA Storage Technology
Another potentially important issue is that Serial Attached SCSI (SAS) connec- tors permit attachment of SATA drives, and supports the SATA protocol. This chapter introduces the major features of the SATA II specification.
Performance and Reliability
Three notable features introduced with the SATA II specification improve per- formance and/or reliability over the previous versions:
• SATA Generation 2 transmission rates (3Gb/s)