Figure 6.18: A picture of an FPGA board
6.4
Control software implementation
To control the hardware component described earlier, control software is implemented which is executed during an ISR in the DSP. When the interrupt signal is received, the ISR is triggered. In the ISR, information about the system such as the cell capacitor voltages, grid voltages, grid currents, grid voltage reference angle, θ, and system DC bus voltage are obtained from the A/D converters. The acquired system information is checked for trip conditions (software trip) to ensure the converter is operating in a safe mode. During start-up, the converter is then operated in a default pre-charge mode, where all the individual chainlink converter cell capacitors are charged to the nominal voltage level as described in 6.3.2. After pre-charging the cell capacitors, the pre-charge circuit is disconnected by disabling the pre-charge contactor (DC1)
and enabling the DC bus contactor (DC2) to connect the power converter to the
DC circuit. At this point the converter operates in ‘port’ mode:-equal numbers of chainlink cells in each chainlink are turned ON in an alternate order to maintain the DC bus voltage. In the grid synchronisation mode, the grid voltage reference angle, θ, is obtained. θ is used to transform the grid voltages and currents to the dq rotating
reference frame for the implementation of the AC/DC power flow described in Figure 6.19.
Figure 6.19: Vector control structure as implemented in DSP
The grid voltage reference angle, θ, and the grid voltage amplitude Vsd are used to
modulate the converter. When the converter is synchronised with the grid network, the AC contactor is closed to connect the power converter to the grid under zero power transfer conditions. Figure 6.20 shows a flow diagram of the ISR execution. During the ‘enable converter control’ block in the flow diagram in Figure 6.20, the control schemes for the integration of the power converter with the AC network discussed in Chapter 4 are implemented. The control involves:
• individual chainlink cell voltage control • total chainlink voltage control
• modulation ratio control • AC/DC power flow control
In the individual chainlink cell voltage control, a sorting algorithm returns the position of each chainlink cell for the converter chainlink waveform generation. The position
6.4. CONTROL SOFTWARE IMPLEMENTATION 152
Figure 6.20: A flow diagram illustrating the sequence of execution of the control software
of the chainlink cells are assigned from zero (0) to (n-1). The algorithm for each chainlink is executed at a predetermined time instant. In the DSP, the grid voltage reference angle is used to determine the sorting instant. Theoretically, additional resources would be required to reassign cells with equal capacitor voltage amplitudes. However, due to the data acquisition process, A/D conversion, and the representation of the acquired data using floating point encoding, the likelihood of two cells reading an equivalent voltage is very small. Therefore, this stage of the sorting algorithm, implemented in simulation, has not been implemented in the experimental work. A digital cascade PI control system ensure the total chainlink voltage is maintained. The modulation ratio control is implemented to maintain the DC bus voltage while the converter operates with a variable fundamental phase voltage amplitude, bVc.
6.5
Conclusions
A small scale laboratory prototype of the PH-M2L-VSC constructed to validate the operation of the converter has been discussed. Design considerations for the selection of components for the power converter has been presented. The control platform, control hardware and data acquisition system have been discussed. The sequence of control algorithm implementation in the DSP and the modulation signal generation in the FPGA has also been outlined.
Chapter 7 will present some experimental results validating the designed power con- verter and control methods. The experimental results obtained are compared with simulation results from a small scale converter of similar rating as the prototype converter.
Chapter 7
Experimental Results
7.1
Introduction
This chapter presents some results obtained from the experimental power converter discussed in Chapter 6. Results have been obtained at various operating conditions during construction. Test results are obtained for the power converter operating in the following modes:
• Inverting into an RL load without modulation ratio control • Inverting into an RL load with modulation ratio control • Connected to the grid for bidirectional power flow validation
A simulation model of similar rating to the small scale laboratory prototype described in Chapter 6 is implemented with the P LECSr simulation package. The experimen-
tal results obtained are compared with the simulation results. Ideal IGBT modules (with their associated anti parallel diodes) and passive components are used in the simulation model. The IGBT modules used in the experimental laboratory prototype
have a series voltage drop of 2.5V at nominal operating conditions. The effect of the device series voltage drop becomes appreciable when it is significant compared to the test voltage. The effect of the non-ideal power electronic switches and the dead time introduced by the control circuit on the experimental results are discussed in Section 7.3.
The experimental results are obtained from the test system using 14 bit analogue to digital (A/D) converter channels on the FPGA boards, and a LeCroy WaveSurfer 424 Oscilloscope via a combination of current probes and differential voltage probes.