1.2.2 VSB/SECONDARY timeout bus error . . 1-3 1.2.2.1 Register CTL15 . . . 1-3 1.2.3 Bus error on parity error detection 1-4 1.2.4 VMEbus timeout bus error . . . 1-4 1.2.4.1 Register CTL16 . . . 1-5 1.2.5 Unaligned RMW cycle to VME . . . . 1-5 1.2.6 LONG timeout . . . 1-5
2. RESET FUNCTION . . . 2-1
2.1 GATE ARRAY RESET . . . 2-1
2.2 VMEbus RESET . . . 2-2
2.3 PROCESSOR RESET . . . 2-2
2.4 RESET SOURCES . . . 2-3 2.4.1 Power-up Input . . . 2-3 2.4.2 Reset Key Input . . . 2-3 2.4.3 Local Switch Reset . . . 2-3 2.4.4 Processor Opcode Reset . . . 2-4 2.4.4.1 Register CTL9 . . . 2-4 2.4.5 CPU Reset Call . . . 2-5 2.4.6 VME Reset Call . . . 2-5 2.4.6.1 Register CTL2 . . . 2-6 2.4.7 SYSRESET* Signal From VME . . . 2-6
2.5 RESET SOURCE READOUT LOCATIONS . . . 2-7
3. ACFAIL Handler Option . . . 3-1
3.1 Register CTL8 . . . 3-2
4. SYSFAIL . . . 4-1
4.1 SYSFAIL Input . . . 4-1 4.1.1 Register SFAILINPIN . . . 4-1
4.2 SYSFAIL Output . . . 4-2 4.2.1 Bootsysfail Bit BSYSBIT . . . 4-2 4.2.1.1 Register CTL8 . . . 4-3 4.2.1.2 Register SPECIAL . . . . 4-4 4.2.2 Softsysfail Bit SSYSBIT . . . 4-5 4.2.2.1 Register CTL8 . . . 4-5 4.2.3 Watchdog Sysfail . . . 4-5
TABLE OF CONTENTS (cont’d)
5. LOCAL SWITCH Input . . . 5-1
6. PARITY SUPPORT . . . 6-1
6.1 PARITY GENERATION/CHECK . . . 6-1 6.1.1 Registers CTL2 . . . 6-1 6.1.2 Register CTL2 . . . 6-2
6.2 PARITY ERROR EVALUATION . . . 6-3 6.2.1 Register CTL16 . . . 6-3 6.2.2 PARITY ERROR OPTION A . . . 6-4 6.2.3 PARITY ERROR OPTION B . . . 6-5
6.3 PARITY ERROR ADDRESS READOUT . . . 6-6
1. BUS ERROR GENERATION
The BUS ERROR Logic of the gate array supports bus error generation for the VMEbus as well as for the local processor. The BERRVO output provides the active low error termination signal for the VMEbus.
On the BERRVI input, the gate array detects when a bus error condition occurred on the VMEbus.
The BERRC signal is generated as an active low bus error signal for the local processor. This signal is also generated for the gate array internal DMA controller.
1.1 BUS ERROR GENERATION TO VME
The gate array drives the signal BERRVO low for a VMEbus error termination in the following cases:
a. Bus error during an FMB cycle
b. Bus error due to a parity error detection c. Bus error due to a VMEbus timeout
1.1.1 FMB bus error
If the gate array is addressed in a FORCE Message Broadcast cycle and the message cannot be stored because of a full FMB fifo, the BERRVO signal will be asserted. Please refer to the FMB section of this manual for more details.
1.1.2 Bus error on parity error detection
The gate array drives the VME bus error signal BERRVO, if the internal parity logic detects an error during a VME access to the local main memory.
The generation of the VME bus error signal due to a parity error detection assumes that the gate array is programmed to support the shared memory structure and that one of the parity error options (Option A or B) is enabled.
1.1.3 VME timeout bus error
A timeout bus error is generated to the VMEbus to terminate a cycle which addresses a nonpresent location or a device which does not respond.
The BERRVO signal is driven if the device does not respond within a defined time.
The timeout is monitored by the gate array’s internal VMEbus timeout counter which is restarted on CPU accesses and DMA controller accesses to the VMEbus.
Please refer to chapter "VME bus access timeout" later in this section.
1.2 BUS ERROR GENERATION FOR THE CPU AND DMA CONTROLLER
The gate array indicates a bus error to the processor or to the DMA controller in the following cases:
a. Bus error due to an ONBOARD access timeout
b. Bus error due to a VSB/SECONDARY bus access timeout c. Bus error due to a PARITY error detection
d. Bus error due to a VMEbus access timeout
e. Bus error due to an UNALIGNED RMW cycle to VME f. Bus error due to a LONG timeout.
1.2.1 Onboard timeout Bus error
A timeout counter is provided inside the gate array for local processor accesses to the MAIN memory decoding area, the USER Eprom area or the LOCAL I/O area.
The timeout counter for onboard accesses starts counting when the gate array samples a low on the ASCPU input signal. In addition, the decoding logic of the gate array has to decode the respective decoding area.
Accesses by the DMA controller to the MAIN memory will also start the timeout counter for onboard accesses.
The Local Bus Error counter of the gate array will terminate the current cycle after 16 microseconds, driving the BERRC output signal low. This action will not take place if the cycle is terminated regularly.
1.2.2 VSB/SECONDARY timeout bus error
If the gate array decodes an access to the VSB bus or to the SECONDARY bus address ranges, the VSB/SECONDARY bus timeout counter is started.
The current cycle will be terminated with a bus error by the VSB/SECONDARY bus timeout counter after the bus error time has elapsed. The gate array finishes the cycle by asserting its BERRC output low.
The VSB/SECONDARY timeout counter is not only started if the processor executes cycles to the secondary or the VSB bus, but also if the DMA controller accesses these areas.
Using bits 6 and 7 in the CTL15 register, the bus error timeout can be set to 16, 1000 or 64000 microseconds or can be disabled.
1.2.2.1 Register CTL15
Register Mnemonic Address R/W Default Control 15 Register CTL15 $FFD00358 R/W $00
Format of CTL15
7 6 5 4 3 2 1 0