Conventional CMOS rectifier

A variety of conventional full wave rectifier have been addressed in [8][23] [7] [20] [10] [21] [11]. A conventional CMOS rectifier circuit [11], which is composed of series connection of diode-connected NMOS and PMOS transistors is shown below. The RF input is applied through the coupling capacitor Cc. During the positive

Figure 3.4. Conventional CMOS rectifier circuit[21].

half cycle of the RF voltage signal, forward current flows to the output load. When negative half cycle of the RF voltage signal is applied, almost no current flows. The output voltage that is developed across the load is given as,

Vout = 2Vrf− Vdrop (3.2)

Most of the power losses of the integrated rectifier circuit originate from the on-resistance of the transistor. The PCE of the rectifier circuit is affected by circuit topology, diode parameters, and input RF signal level [20][10]. Small ON- resistance and small reverse leakage current are the main parameters of the MOS diode which can increase the PCE of the rectifier. Generally, small on-resistance of the MOS-diode is achieved by small turn on voltage of the transistor that is the threshold voltage of the transistor. It is thus desirable for the threshold voltage of the transistor to be as small as possible to decreases the losses in the rectifier circuit. The voltage drop across a MOS diode is given as,

δV = Vth+

s 2LI

CoxW µ (3.3)

where, W and L are the width and length of the transistor, I is the current flowing and Cox is process related product and Vthis the threshold voltage of the transis-

tor. The voltage drop not only related to the threshold voltage, but also depend on the overload voltage, which linearly increases with square root of the current. As the threshold voltage is the main parameter which can degrade the perfor- mance of the rectifier, appropriate Vth-cancellation mechanism is applied, which are External-Vth-cancellation (EVC) scheme [21], Self-Vth-cancellation (EVC) scheme [11] [20], and Internal-Vth-cancellation (IVC) scheme [17].

External-Vth-cancellation (EVC) scheme

The output voltage that can be obtained from conventional rectifier as discussed above is given as:

Vout= 2 ∗ (Vrf− Vth) (3.4)

Maximum output voltage is obtained when threshold voltage is negligible. In this scheme a bias voltage is added between the gate and drain of the transistor.

Figure 3.5. External-Vth-cancellation CMOS rectifier circuit[17].

Thereby the threshold voltage changes to Vth− Vbias. The output voltage can be

rewritten as:

Vout= 2 ∗ (Vrf− Vth+ Vbias) (3.5)

The threshold voltage is expected to reduce to zero when Vth is nearly equal to

Vbias, then the output voltage can be approximated as,

Vout= 2Vrf (3.6)

Therefore, it is possible to rectify small RF signals with this structure. However, it is not optimal due to the additional batteries used.

Self-Vth-cancellation (SVC) scheme

The developed self-Vth-cancellation (SVC) CMOS rectifier circuit [11] [20] is shown figure 3.6. In self-Vth-cancellation rectifier, the gate of the NMOS and PMOS transistors are cross-connected such that the NMOS transistor and The transistors

Figure 3.6. Self-Vth-cancellation CMOS rectifier circuit[21].

are connected to the output terminal and ground terminal respectively as shown in the figure. This connection increases the gate-source voltage of the transistor which equivalently decreases the threshold voltage.

This scheme is simple and does not require any additional power circuitry. Gate-source voltages of the NMOS and PMOS transistors are statically biased using the output DC voltage, thus reducing the effective Vth of the MOS transis-

tors [20], which result in large PCE. In this configuration, the energy loss mostly depends on the on-resistance of the transistor. When the threshold voltage is too small, it may cause reverse leakage current which will reduce the PCE. Hence it is not possible to achieve small on-resistance and small leakage current in self-Vth- cancellation rectifier. As a result, PCE of the SVC rectifier circuit will first increase with the increase in input power, but then decrease with the further increase in input power, exhibiting some peak value in between [10].

CMOS differential rectifier

According to SVC scheme rectifier it is not possible to achieve small on-resistance and small leakage current simultaneously. In order to solve the problem differential-

Figure 3.7. Differential-drive CMOS rectifier[21].

drive CMOS rectifier circuit has been developed [20] [10]. It consist of a cross- coupled differential CMOS with a bridge structure. In this differential structure, the gate of the transistor is biased by a differential signal. From the figure, Vxand

Vy are the differential input RF signal. When Vx is negative then the transistor

MN1 is forward biased and when Vy is positive which correspond to positive gate

voltage bias of MN1 transistor, which decreases the threshold voltage of the tran- sistor. This results in small on-resistance. Whereas, when Vx is positive and Vy

is negative, the transistor is reversed biased and the gate voltage decreases which increase the threshold voltage, resulting in reduction in reverse leakage current.

This kind of rectifier performs better than the MOS-diode based rectifier. It is also called four-transistor cell according to [14] and called negative voltage converter according to [19]. The structure consists of combination of two cross- connected gate structure which provide complimentary bridge rectifier. In the circuit, the PMOS transistor delivers highest voltage to the load, whereas the NMOS-transistor provide the lowest voltage. The transistor operates in the triod

region which behaves as a switch, thereby having smaller voltage drop compared to MOS-diode. The output voltage is given as,

VDC = 2VRF− Vdrop (3.7)

where, VRF is the amplitude of the differential signals and Vdrop is the losses

due to swich resistance and reverse conduction. The maximum output voltage is limited to 2VRF. To increase the output voltage, N cells of the structure can be

cascaded. Differentials signal of the first stage is directly connected to to the RF source whereas, the proceeding stages are capacitivly coupled to the RF source. This structure behaves as a charge pump voltage multiplier [14], as the expected output voltage at the N’th stage is VDC = N (2VRF − Vdrop) but in practice the

output voltage is lower because the Vdropincreases with the increase of the number

of cells due to increase of the body bias of the transistor.