Critical path delay

The critical path delay tcritlimits the maximum frequency of a circuit and increases

with additional serial logic on the critical path. In what follows, we first determine LTMR’s then PBED’s critical path delay, and then compare them.

LTMR

In LTMR, every bit must be decoded by a majority voter (MAJ3) before it is propa- gated to the combinational logic, which causes an extra delay. Consequently the actual critical path delay tcrit,bareis extended by the propagation delay of the ma-

jority voter. The subscriptpdstands for propagation delay.

tcrit+,LTMR = tpd,MAJ3 (4.1)

FF LTMR FF FF majority voter FF tcrit,bare tcrit,LTMR tcrit+,LTMR

Figure 4.4: The critical path overhead of the LTMR visualized. Critical paths of the bare and LTMR applied circuit are denoted as tcrit,bareand tcrit,LTMR. Note that

even tcritliterally denotes the maximum time duration that a flipflop output sig-

nal requires to reach another flipflop, in this figure, tcritdenotes the path that this

critical flipflop output signal travels.

PBED

In PBED, there are two critical path candidates:

1. the actual critical path plus the overhead added serially by PBED, i.e., the critical path of the bare circuit plus the parity generation path, tcrit,PBED,1

2. a newly created parallel path by PBED, the parity check and the cluster error signal reduction path, tcrit,PBED,2

These two paths are visualized in figure 4.5.

The first path delay can be calculated as follows: The parity has to be gener- ated before the combinational signals are registered. The propagation delay of the gate XORpgis called tpd,XORpg.

tcrit+,PBED,1= tpd,XORpg (4.2) The second path tcrit,PBED,2consists of the XORpcand ORrdc.

tcrit,PBED,2= tpd,XORpc+ tpd,ORrdc (4.3) The gates XORpc, XORpgand ORrdccan have more than three inputs, so they

will be synthesized as a tree of LUTs on the ProASIC3. The synthesis of a gate with

sinputinputs to a tree with a depth of d is shown in figure 4.6.

The propagation delay generated by a gate with an input size sinputis called

tpd(gate, sinput)and can be calculated by determining the depth d of the tree and

4.2. ANALYTICAL EVALUATION 51

Figure 4.5: The two critical path candidates in direct PBED, tcrit,PBED,1 and

tcrit,PBED,2. Note that tcrit,PBED,1is generated by adding the critical path overhead

of PBED tcrit+,PBED,1to the existing critical path of the target circuit tcrit,barewhile

tcrit,PBED,2is newly generated by PBED.

// sinput LUT LUT LUT LUT LUT LUT LUT depth 1 … d− 1 d 1 2. .. .. . sinput

Figure 4.6: The figure shows how a gate with input size of sinputis mapped to an

FPGA architecture with three-input LUTs. After mapping, a LUT tree with a depth of d =⌈log3sinput⌉ is created. Note that if sinputis not a power of three, then not

OR3 for an OR gate), as the interconnect delays are not considered:

tpd(gate, sinput) = dgate· tpd,macro

=⌈log3sinput⌉ · tpd,macro

(4.4)

With eq. 4.4, the propagation delays of the three defined gates can be calculated:

tpd,XORpg =⌈log3(scl− 1)⌉ · tpd,XOR3 (4.5)

tpd,XORpc=⌈log3scl⌉ · tpd,XOR3 (4.6)

tpd,ORrdc=⌈log3ccl⌉ · tpd,OR3

= ⌈ log₃⌈cFF,bare scl ⌉⌉ · tpd,OR3 (4.7)

With equations 4.5 to 4.7, we can finally calculate the critical paths for PBED by only using our input parameter variables scland cFF,bare.

The critical path delays tcrit+,PBED,1and tcrit,PBED,2have the input parameter vari-

ables scland cFF,bare. The remaining input parameters, i.e., gate propagation de-

lays, are assumed to be constant values. Propagation delay of the macros are de- pendent on environment factors like the temperature, but we assume a constant environment in our analysis. Consequently, only scland cFF,barelimit the maximum

frequency of the circuit.

In ProASIC3, at a junction temperature of 70◦C and worst-case supply voltage 1.14 V, tpd,MAJ3, and tpd,XOR3are 1.09 ns, and 1.37 ns respectively [Micr15a]. The

propagation delay tpd,OR3was neither available in the datasheet or macro library

documentation. We assume the value of tpd,OR3 = 0.777ns, which is taken from

the timing report of a layouted netlist which uses the primitive OR3. With these data the critical path caused by the flipflops and combinational elements can be calculated for various scland cFF,bareparameters.

Comparison

Table 4.1 shows the critical path delays tcrit+,1and tcrit,2for various values of the in-

put parameter (x, y). The parameters scland cFF,bareare determined using (x, y),

where scl= 3x, cluster count ccl = 3yand flipflop count in the bare circuit cFF,bare=

(scl− 1) · ccl. With increasing depth of XORpg, tcrit+,1grows for PBED, i.e., every

time when sclreaches a higher power of 3. The additional path delay tcrit+,1 of

LTMR is independent of the input parameters. For scl = 3LTMR and PBED have a

similar critical path overhead. PBED has additionally the tcrit+,2, which grows with

4.2. ANALYTICAL EVALUATION 53

tcrit+,1(ns) tcrit,2(ns)

(x, y) scl ccl cFF,bare LTMR PBED PBED

(1,2) 3 9 18 1.09 1.37 2.92 (1,3) 3 27 54 1.09 1.37 3.7 (1,4) 3 81 162 1.09 1.37 4.48 (2,2) 9 9 72 1.09 2.74 4.29 (2,3) 9 27 216 1.09 2.74 5.07 (2,4) 9 81 648 1.09 2.74 5.85 (3,2) 27 9 234 1.09 4.11 5.66 (3,3) 27 27 702 1.09 4.11 6.44 (3,4) 27 81 2106 1.09 4.11 7.22

Table 4.1: Critical path impacts of LTMR and PBED for different numbers of appli- cation flipflops in the circuit and cluster sizes

Compared to the tcrit+,PBED,1, which is always relative to the existing critical

path tcrit,bare, tcrit,PBED,2is generated in parallel to the bare circuit. Due to this rea-

son, tcrit,PBED,2stays uncritical up to a certain depth of parity check and reduction

gates.