There are also ten user-controllable LEDs connected to FPGA on the board. Each LED is driven directly by a pin on the Cyclone V FPGA; driving its associated pin to a high logic level turns the LED on, and driving the pin low turns it off. Figure 3-8 shows the connections between LEDs and Cyclone V FPGA. Table 3-2, Table 3-3 and Table 3-4 list the pin assignment of user push-buttons, switches, and LEDs.
Figure 3-8 Connections between the LEDs and Cyclone V FPGA
Table 3-2 Pin Assignment of Push-buttons
Signal Name FPGA Pin No. Description
KEY0 PIN_U7 Push-button[0]
KEY1 PIN_W9 Push-button[1]
KEY2 PIN_M7 Push-button[2]
KEY3 PIN_M6 Push-button[3]
RESET_N PIN_P22 Push-button which connected to DEV_CLRN Pin of FPGA
Table 3-3 Pin Assignment of Slide Switches
Signal Name FPGA Pin No. Description
SW0 PIN_U13 Slide Switch[0]
SW1 PIN_V13 Slide Switch[1]
SW2 PIN_T13 Slide Switch[2]
Table 3-4 Pin Assignment of LEDs
Signal Name FPGA Pin No. Description
LEDR0 PIN_AA2 LED [0] Cyclone V FPGA. The segment can be turned on or off by applying a low logic level or high logic level from the FPGA, respectively.
Each segment in a display is indexed from 0 to 6, with corresponding positions given in Figure 3-9.
Table 3-5 shows the pin assignment of FPGA to the 7-segment displays.
Figure 3-9 Connections between the 7-segment display HEX0 and the Cyclone V FPGA
Table 3-5 Pin Assignment of 7-segment Displays
Signal Name FPGA Pin No. Description
HEX02 PIN_W22 Seven Segment Digit 0[2]
HEX03 PIN_W21 Seven Segment Digit 0[3]
HEX04 PIN_Y22 Seven Segment Digit 0[4]
HEX05 PIN_Y21 Seven Segment Digit 0[5]
HEX06 PIN_AA22 Seven Segment Digit 0[6]
HEX10 PIN_AA20 Seven Segment Digit 1[0]
HEX11 PIN_AB20 Seven Segment Digit 1[1]
HEX12 PIN_AA19 Seven Segment Digit 1[2]
HEX13 PIN_AA18 Seven Segment Digit 1[3]
HEX14 PIN_AB18 Seven Segment Digit 1[4]
HEX15 PIN_AA17 Seven Segment Digit 1[5]
HEX16 PIN_U22 Seven Segment Digit 1[6]
HEX20 PIN_Y19 Seven Segment Digit 2[0]
HEX21 PIN_AB17 Seven Segment Digit 2[1]
HEX22 PIN_AA10 Seven Segment Digit 2[2]
HEX23 PIN_Y14 Seven Segment Digit 2[3]
HEX24 PIN_V14 Seven Segment Digit 2[4]
HEX25 PIN_AB22 Seven Segment Digit 2[5]
HEX26 PIN_AB21 Seven Segment Digit 2[6]
HEX30 PIN_Y16 Seven Segment Digit 3[0]
HEX31 PIN_W16 Seven Segment Digit 3[1]
HEX32 PIN_Y17 Seven Segment Digit 3[2]
HEX33 PIN_V16 Seven Segment Digit 3[3]
HEX34 PIN_U17 Seven Segment Digit 3[4]
HEX35 PIN_V18 Seven Segment Digit 3[5]
HEX36 PIN_V19 Seven Segment Digit 3[6]
HEX40 PIN_U20 Seven Segment Digit 4[0]
HEX41 PIN_Y20 Seven Segment Digit 4[1]
HEX42 PIN_V20 Seven Segment Digit 4[2]
HEX43 PIN_U16 Seven Segment Digit 4[3]
HEX44 PIN_U15 Seven Segment Digit 4[4]
HEX45 PIN_Y15 Seven Segment Digit 4[5]
HEX46 PIN_P9 Seven Segment Digit 4[6]
HEX50 PIN_N9 Seven Segment Digit 5[0]
HEX51 PIN_M8 Seven Segment Digit 5[1]
HEX52 PIN_T14 Seven Segment Digit 5[2]
HEX53 PIN_P14 Seven Segment Digit 5[3]
HEX54 PIN_C1 Seven Segment Digit 5[4]
HEX55 PIN_C2 Seven Segment Digit 5[5]
3. 3 . 4 4 Cl C l oc o ck k Ci C i rc r cu ui i tr t r y y
Figure 3-10shows the clock circuit of DE0-CV Board, the crystal 50 MHz buffered to four 50MHz clock. The associated pin assignment for clock inputs to FPGA I/O pins is listed in Table 3-6.
Figure 3-10 Clock circuit of the FPGA Board
Table 3-6 Pin Assignment of Clock Inputs
Signal Name FPGA Pin No. Description
CLOCK_50 PIN_M9 50 MHz clock input(Bank 3B) CLOCK2_50 PIN_H13 50 MHz clock input(Bank 7A) CLOCK3_50 PIN_E10 50 MHz clock input(Bank 8A) CLOCK4_50 PIN_V15 50 MHz clock input(Bank 4A)
3. 3 . 5 5 Us U si i ng n g 2 2x x2 2 0 0 G GP PI IO O E Ex xp pa an ns si i on o n H He ea ad de er r s s
The board has two 40-pin expansion headers. Each header has 36 user pins connected directly to the Cyclone V FPGA. It also comes with DC +5V (VCC5), DC +3.3V (VCC3P3), and two GND pins.
Both 5V and 3.3V can provide a total of 5W power.
Each pin on the expansion headers is connected to two diodes and a resistor for protection against high or low voltage level. Figure 3-11 shows the protection circuitry applied to all 2x36 data pins.
Figure 3-11 shows the related schematics. Table 3-7 shows the pin assignment of two GPIO headers.
Figure 3-11 Connections between the GPIO header and Cyclone V FPGA
Figure 3-12 I/O distribution of the expansion headers
Table 3-7 Pin Assignment of Expansion Headers
GPIO_0_D7 PIN_K22 GPIO Connection 0[7]
GPIO_0_D8 PIN_M20 GPIO Connection 0[8]
GPIO_0_D9 PIN_M21 GPIO Connection 0[9]
GPIO_0_D10 PIN_N21 GPIO Connection 0[10]
GPIO_0_D11 PIN_R22 GPIO Connection 0[11]
GPIO_0_D12 PIN_R21 GPIO Connection 0[12]
GPIO_0_D13 PIN_T22 GPIO Connection 0[13]
GPIO_0_D14 PIN_N20 GPIO Connection 0[14]
GPIO_0_D15 PIN_N19 GPIO Connection 0[15]
GPIO_0_D16 PIN_M22 GPIO Connection 0[16]
GPIO_0_D17 PIN_P19 GPIO Connection 0[17]
GPIO_0_D18 PIN_L22 GPIO Connection 0[18]
GPIO_0_D19 PIN_P17 GPIO Connection 0[19]
GPIO_0_D20 PIN_P16 GPIO Connection 0[20]
GPIO_0_D21 PIN_M18 GPIO Connection 0[21]
GPIO_0_D22 PIN_L18 GPIO Connection 0[22]
GPIO_0_D23 PIN_L17 GPIO Connection 0[23]
GPIO_0_D24 PIN_L19 GPIO Connection 0[24]
GPIO_0_D25 PIN_K17 GPIO Connection 0[25]
GPIO_0_D26 PIN_K19 GPIO Connection 0[26]
GPIO_0_D27 PIN_P18 GPIO Connection 0[27]
GPIO_0_D28 PIN_R15 GPIO Connection 0[28]
GPIO_0_D29 PIN_R17 GPIO Connection 0[29]
GPIO_0_D30 PIN_R16 GPIO Connection 0[30]
GPIO_0_D31 PIN_T20 GPIO Connection 0[31]
GPIO_0_D32 PIN_T19 GPIO Connection 0[32]
GPIO_0_D33 PIN_T18 GPIO Connection 0[33]
GPIO_0_D34 PIN_T17 GPIO Connection 0[34]
GPIO_0_D35 PIN_T15 GPIO Connection 0[35]
GPIO_1_D0 PIN_H16 GPIO Connection 1[0]
GPIO_1_D1 PIN_A12 GPIO Connection 1[1]
GPIO_1_D2 PIN_H15 GPIO Connection 1[2]
GPIO_1_D3 PIN_B12 GPIO Connection 1[3]
GPIO_1_D4 PIN_A13 GPIO Connection 1[4]
GPIO_1_D5 PIN_B13 GPIO Connection 1[5]
GPIO_1_D6 PIN_C13 GPIO Connection 1[6]
GPIO_1_D7 PIN_D13 GPIO Connection 1[7]
GPIO_1_D8 PIN_G18 GPIO Connection 1[8]
GPIO_1_D9 PIN_G17 GPIO Connection 1[9]
GPIO_1_D10 PIN_H18 GPIO Connection 1[10]
GPIO_1_D11 PIN_J18 GPIO Connection 1[11]
GPIO_1_D12 PIN_J19 GPIO Connection 1[12]
GPIO_1_D13 PIN_G11 GPIO Connection 1[13]
GPIO_1_D14 PIN_H10 GPIO Connection 1[14]
GPIO_1_D15 PIN_J11 GPIO Connection 1[15]
GPIO_1_D18 PIN_J13 GPIO Connection 1[18]
GPIO_1_D19 PIN_L8 GPIO Connection 1[19]
GPIO_1_D20 PIN_A14 GPIO Connection 1[20]
GPIO_1_D21 PIN_B15 GPIO Connection 1[21]
GPIO_1_D22 PIN_C15 GPIO Connection 1[22]
GPIO_1_D23 PIN_E14 GPIO Connection 1[23]
GPIO_1_D24 PIN_E15 GPIO Connection 1[24]
GPIO_1_D25 PIN_E16 GPIO Connection 1[25]
GPIO_1_D26 PIN_F14 GPIO Connection 1[26]
GPIO_1_D27 PIN_F15 GPIO Connection 1[27]
GPIO_1_D28 PIN_F13 GPIO Connection 1[28]
GPIO_1_D29 PIN_F12 GPIO Connection 1[29]
GPIO_1_D30 PIN_G16 GPIO Connection 1[30]
GPIO_1_D31 PIN_G15 GPIO Connection 1[31]
GPIO_1_D32 PIN_G13 GPIO Connection 1[32]
GPIO_1_D33 PIN_G12 GPIO Connection 1[33]
GPIO_1_D34 PIN_J17 GPIO Connection 1[34]
GPIO_1_D35 PIN_K16 GPIO Connection 1[35]
3. 3 . 6 6 Us U si i ng n g V VG GA A
The DE0-CV board includes a 16-pin D-SUB connector for VGA output. The VGA synchronization signals are provided directly from the Cyclone V FPGA, and a 4-bit DAC using resistor network is used to produce the analog data signals (red, green, and blue). The associated schematic is given in Figure 3-13 and can support standard VGA resolution (640x480 pixels, at 25 MHz).
The timing specification for VGA synchronization and RGB (red, green, blue) data can be easily found on website nowadays. Figure 3-13 illustrates the basic timing requirements for each row (horizontal) displayed on a VGA monitor. An active-low pulse of specific duration is applied to the horizontal synchronization (hsync) input of the monitor, which signifies the end of one row of data and the start of the next. The data (RGB) output to the monitor must be off (driven to 0 V) for a time period called the back porch (b) after the hsync pulse occurs, which is followed by the display interval (c). During the data display interval the RGB data drives each pixel in turn across the row being displayed. Finally, there is a time period called the front porch (d) where the RGB signals must again be off before the next hsync pulse can occur. The timing of vertical synchronization (vsync) is similar to the one shown in Figure 3-14, except that a vsync pulse signifies the end of one frame and the start of the next, and the data refers to the set of rows in the frame (horizontal timing). Table 3-8 and Table 3-9 show different resolutions and durations of time period a, b, c, and d for both horizontal and vertical timing.
The pin assignments between the Cyclone V FPGA and the VGA connector are listed in Table
Configuration Resolution(HxV) a(lines) b(lines) c(lines) d(lines) Pixel clock(MHz)
VGA(60Hz) 640x480 2 33 480 10 25
Table 3-10 Pin Assignment of VGA
Signal Name FPGA Pin No. Description
VGA_R0 PIN_A9 VGA Red[0]
The DE0-CV board comes with a standard PS/2 interface and a connector for a PS/2 keyboard or mouse. Figure 3-15 shows the connection of PS/2 circuit to the FPGA. Users can use the PS/2 keyboard and mouse on the DE0-CV board simultaneously by a PS/2 Y-Cable, as shown in Figure 3-16. Instructions on how to use PS/2 mouse and/or keyboard can be found on various educational websites. The pin assignment associated to this interface is shown in Table 3-11.
Note: If users connect only one PS/2 equipment, the PS/2 signals connected to the FPGA I/O should be “PS2_CLK” and “PS2_DAT”.
Figure 3-16 Y-Cable for using keyboard and mouse simultaneously
Table 3-11 Pin Assignment of PS/2
Signal Name FPGA Pin No. Description
PS2_CLK PIN_D3 PS/2 Clock
PS2_DAT PIN_G2 PS/2 Data
PS2_CLK2 PIN_E2 PS/2 Clock (reserved for second PS/2 device) PS2_DAT2 PIN_G1 PS/2 Data (reserved for second PS/2 device)
3. 3 . 8 8 Mi M i cr c ro o S S D- D - Ca C ar rd d So S oc ck ke et t
The development board supports Micro SD card interface using x4 data lines. Figure 3-17 shows the related signals connections between the SD Card and Cyclone V FPGA and Figure 3-18 shows micro SD card plug-in position.
Finally, Table 3-12 lists all the associated pins.
Figure 3-18 Micro SD Card
Table 3-12 Pin Assignment of Micro SD Card Socket
Signal Name FPGA Pin No. Description
SD_CLK PIN_H11 Serial Clock
SD_CMD PIN_B11 Command, Response
SD_DATA0 PIN_K9 Serial Data 0
SD_DATA1 PIN_D12 Serial Data 1
SD_DATA2 PIN_E12 Serial Data 2
SD_DATA3 PIN_C11 Serial Data 3
3. 3 . 9 9 Us U si i ng n g S S DR D RA AM M
The board features 64MB of SDRAM with a single 64MB (32Mx16) SDRAM chip. The chip
Figure 3-19 Connections between the FPGA and SDRAM
Table 3-13 Pin Assignment of SDRAM
Signal Name FPGA Pin No. Description
DRAM_ADDR0 PIN_W8 SDRAM Address[0]
DRAM_DQ10 PIN_AA8 SDRAM Data[10]
DRAM_DQ11 PIN_AA7 SDRAM Data[11]
DRAM_DQ12 PIN_V10 SDRAM Data[12]
DRAM_DQ13 PIN_V9 SDRAM Data[13]
DRAM_DQ14 PIN_U10 SDRAM Data[14]
DRAM_DQ15 PIN_T9 SDRAM Data[15]
DRAM_BA0 PIN_T7 SDRAM Bank Address[0]
DRAM_BA1 PIN_AB7 SDRAM Bank Address[1]
DRAM_LDQM PIN_U12 SDRAM byte Data Mask[0]
DRAM_UDQM PIN_N8 SDRAM byte Data Mask[1]
DRAM_RAS_N PIN_AB6 SDRAM Row Address Strobe DRAM_CAS_N PIN_V6 SDRAM Column Address Strobe
DRAM_CKE PIN_R6 SDRAM Clock Enable
DRAM_CLK PIN_AB11 SDRAM Clock
DRAM_WE_N PIN_AB5 SDRAM Write Enable
DRAM_CS_N PIN_U6 SDRAM Chip Select