5.4 Delay Cornput.1t.t.ion in t.he ;Bicornponen\ Graph
5.4 Delay Computation in the
~!componentGraph
Delay computation
.
, in the'bicomponent graph of a group G proceeds in two , steps. First, the capacitive loading is computed on each ,articulation point that has• 0 •
an active path to the source. Then, delays in individual bicomponents are computed
.
. and pieced together to obtain deIa~ G..
The computation of capacitive Ioading is done by performing ~a.
depth first traversaI of Bie(G), starting at the source and applying Eq. (5.1). To reflect the dynamic state of'the group, the traversai is cut off at a Rode' Il in bicomponènt b when there is no path from the bieomponent source of b and Il,, The articulation point loading algorithm reads as follows:ARTICULATION-POINT-LOADING (v, bic)
if tJ 18 an articulation point and bic i8 null then load +- Ct)
foreach unmarked bic incident to Il do mark bic
load +-load
+
articulation-point-loading(lI, bic) eiseif tJ ;8 an articulation point then , ,~ lolzd' t - 0
else
load +- Cv '
foreach unmarked active edge vw incident· to v in bic do mark vw
if W ;8 not marked then --mark w
load +- loa'll
+
artieulation-point-loading(w, null) if Il i8 lin articulation point thenC~ +-load
return load •
It is initiated as
Articulation-tio.int-loading( source, null),
o
57
,
(
, \ 6.4 Delay Computation in the Bicomponent Graph
~here, once again, the grou is implicitly determined by the context.
Delaya in Bic(G) e obtained 'br performing a depth first traversai of Bic( G) and computing the delay in r-bico~ponent as if it co~isted of a whole
group: . . " ,
DELA Y-IN-BICOM-GRAPH( a, b, offset) compute-delafl-in-bicom(a, b, offset) foreach child a'
01
b in Bie(G) doforeach child
b' 01
a' in Bic(G) do delall-~n-bicom-graph( a', Il, Toi) The computation o.f' delaya in Bic( a) is initiated as.,
Delafl-jn-bicom-graph(source, b,ource, 0)
"Exeept for the usage of articulation points 'as bicomponent sourçes, the computation of delays in bicomponents ÎB basically the same as in groups. How-ever, single edge bicomponents are given spécial treatment sinee this is " frequently
• a
dccurrmg case:
\
Oompute-delafl-in-bicom (a, b, offset) if b is C'J single edge
av
tbenTv +- RouC!:
+
offset elaesplit b using a as Bource
compute .:nternal capacitive loadinl1 applll Borne relazation algorithm foreach node v::j:. a in b
do-T" +- T"
+
offsetEx. 5.1, at tHe beginning of this Chapter, basie,-lly uses tlïis a.lgorithm.
)
58
o
o
o
5.& Diac:u .. ion
6.6 Discussion
In this chapter, the concept of bicomponent was presented. The bicom-ponent is the minimal subgroup in which delays can be comput~d. Algorithms ta determine bicom:vonents, to compute capacitive loading at articulation points and to compute delays in bicomponents' were presented.
The main' motivation ,fo~ such an approach is 'speed improverA~t. By , reducing the size of the network on which the LM algoritru".. or its derivatives are applied, the cost of ea.ch iteration is reduced, and, hop.ef'W{y, the number of Itera-tions is also reduced. As a ~econdà.ry motivationt it is hoped that the splitting of bicomponents pro duces better jnitial conditions for the iterative algorithms. Thi~
hope is based on the fact that from the bicomponent dccomposition, some nodes (the bicomponent sources) are singled out as non-split table nodes. The set of possible
spHts is therefore reduced. .
So~
o:xperimental data on the use of the bicoU:ponentmethoJ;;--;;te~
senteq. in Chapter 6.
1
1
)
..
c
-
1Chapter
6EXPERIMENTAL RESULTS
~The various methods for computing delays in transistor groups containing loops that were presented in the previous chapters are compared here with respect to two major criteria: computation accuracy and computation speed. Requirements' of accuracy' and speed are often confiicting. The delay computation proQlem is in that respect no different from many other numerical 'Problems. The major trade-offs involved in the choice of a method are made explicit and exemplifie~ by simple circ,uits. This analysis is b,a-sed on the implementation of ~e various met'hods as plug-in modules for the McSLADE switch-Ievelz"imulator.
The chapter starts offwith a brief description of McSLADE, then proceeds to state the experimental procedure used. The core of the chapter consists c;>f the
l '
description and analysis of typical results obtained by applying tIie various methods'
.
-to a set of carefully chosen test circuits. The analysis of the r~lati,!e merits of tie
~,
presented methods is given in the next cpapter and serves as a general conclusion for
" 1
this work.
6.1 ImpIe entation •
The McSLADE simulator !Kho86] is used as the basis of the
implemen-,
"
tation. McSLADE is an experimentaI simulator written in ,~he C programming lan-guage, targetèd at a UNIX system. In its original version; it consista of about
3i
G
A ~
~ $
I.'f'/
,~
o
o
6.1 lmplement.tion lines of code. It..is by no means meant to be user friendlYi its main putpoae ta to )..est
out switch-level algorithms. ) ,
~
,L
The delay computation section of McSLADE is sufficiently decoupled from -the rest of the simulator to make its rewriting possibl€without globally afl'ect~ng the program. However, 'most data structures, in particular the circuit topology descrip-tors (NODE, SWITCH, GROUP) were implemented usi~g arrays, severely limiting
. .
the size of circuits that can .be simulated. Those structures have been redefined us-ing lists, makus-ing surface modifi~ations necessary to the sections on scheduling, logic evaluation, effective·resistance computation and user interface.' The eue of use of the program has also been slightly improved by the addition of a parser for a subset of the SPICE input format. It is now possible to feed exactly the sarne data to both McSLADE and SPICE, thereby greatly fa.cilitating comparison of results. Further, a post-processor for SPICE has been written. Thi~ post-processor converts the SPICE output format to McSLADE format by as"igning a logic value at èach time, for ea.ch analog signal computed by SPICE.
The delay evaluation section has been completely rewritten in or der to
impleme~t ;-he various algorithms proposed in the previoUB chapters. This has been done m..sfu:h a way that the various featurés are independent of one another. Hence, any combinat ion of methods (relaxation method, node splitting method, initial ca-pacitance assignment method and bicoînponent computation method) can be tested.
In order to keep the code modular, alLdecisions on the delay comput,tion method to be used are made before the delay evaluation of a group begins. The appropriate ~
functions ÏIn:plementing the various methods are passed as parameters to the delay evaluation function. With this decision procedure, there is no overhead associated with the choice or IL particular method within the delay evaluatio'n function. AlBo, the program has been written so that intefI!lediate values are observable, if needed.
The delay evaluation portion of the modified McSLADE program comprises approx-imatively 3000 lines qf code.
For all expeÎ\ments performed in this research, the Northern Telecom CMOSIB pro cess was uled. This is the target pro cess for which the technology files 61
\
1 ---~
(
(
)