This chapter aims to define the design goals as well as analyse the fundamental blocks and part sections required for the development of a radio frequency identification system to be implemented for improving access control as discussed in previous chapters. Discussions here are on the architecture design of the RFID reader. Also in view are the functional designs at a lower abstraction level of the different functional blocks of the reader coupled with the algorithm flowchart of the microcontroller.
3.1 Design Goals
The goals of the project need to be defined before an attempt at the construction or in this case an adaptation of a design can begin. The goals set for the project are the following:
i. The construction of a RFID reader that operates within the 125kHz bandwidth that can read or detect a 125kHz tag.
ii. The construction of a reader according to the Frequency Shift Key Modulation pattern of the obtained tags.
iii. The construction of a reader that keeps records of all the enquiries on the reader. These records should be remotely accessible so that they can be audited by a trusted third party. Because of this logging facility the reader won’t require full-time connection to the network infrastructure. This facility increases the flexibility of the reader and allows its application in environments where network connectivity is
Microcontrol
not constantly available, e.g. during flight on an airplane. Obviously, it should not be possible to forge these records in any way.
3.2 Functional Block Diagram
This design which comprise mainly of two parts outside the RFID tag to be obtained is with the motive of achieving the expected read range offered by the 125kHz un-regulated frequency. Notably seen in the depiction above is the freely hanging capacitor that is situated just outside the design. This capacitor, though out of any particular functional block, plays a role of
differentiating the transmitted signal from received signal, so as to eliminate confusion as regards signal reception.
Figure 3.1 Functional Block Diagram for RFID Reader Design
To Access Control Interface
design purpose. Although each individual part of the circuit will be described in detail later, the general idea for circuit operation is as such: The microcontroller provides a timer-driven 125 KHz square wave for the carrier frequency that is sent through the RF choke, which is essentially a passive low-pass filter with steep drop-off to knock out the upper harmonics and leave only a sine wave. Since the reader antenna coil is a series resonant L-C circuit, maximum resonance is achieved at minimum impedance, so it is very important that adequate current amplification is done as to not overdrive the microcontroller. The sine wave is then amplified to maximize current. On the receiving end, the signal is first put through the envelope detection block where it is first half-wave rectified, and is then fed through a half-wave R-C filter to help knock out most of the 125 KHz carrier and detect the envelope signal. This signal is then band-pass filtered using a series of Twin-T active band-pass filters, and low-pass filtered with an active Butterworth filter to further decrease gain in frequencies outside of the 10-20 KHz area and increase gain of the envelope signals such that it saturates the op-amps of the filters. At a final stage the signal is put through the pulse-shaping circuit which comprise of the comparator and resistive divider to produce a nice square wave at logic levels, which are fed to some D-flip flops and a decade counter to extract data from the modulating square waves. The signal is then finally passed on to the microcontroller and processed.
The following are the individual blocks and reasons behind their selection:
i. Microcontroller: Performs digital signal processing, communicates with the host computer and provides the timer driven 125kHz square wave for the carrier frequency using an attached 4MHz crystal oscillator.
ii. RF Choke: Simply a passive low-pass filter whose task is to knock off the upper harmonics of the square wave from the microcontroller and output a clean 125kHz signal.
iii. Carrier Signal Amplifier: In an effort to match impedance with the RFID tag antenna coil and ensure the maximum transfer of power through the antenna coil through magnetic coupling, it is important to amplify the power of the signal while reducing the impedance of the circuit. Hence this component block was attached to the signal before the antenna coil.
iv. Reader Antenna Coil: It is a fundamental principle that when an electric current flows through a conductor, it generates a magnetic field in a direction normal to the direction of the current flowing in the conductor. Because the medium of communication between the reader circuit and tag coil is by magnetic coupling, it was paramount to generate a magnetic field through an antenna at the end of the signal.
Hence this component block of antenna coil need be attached to the tip end of the circuit’s transmitting section.
v. Envelope detection: Since the receive antenna coil is also the transmit antenna coil, a circuit to detect the modulated signal from the tag is attached to receive the backscattering signal and filter some of the 125kHz carrier signal still attached to it.
vi. Filter and Amplifier: To uncover the information on the received signal, there is need to filter the signal and then pass it on through a signal amplifier to boost its strength before signal processing.
vii. Pulse shaping: This component block is required to make the received, filtered and amplified signal digital. This means that we need to make the signal ready for processing by the microcontroller. This is done be pulse shaping the signal into a square wave of digital levels using comparators and digital logic combinations.
viii. Serial Interface: As part of the design goal is to make the reader capable of administration, a serial interface is designed to connect the microcontroller and the processed signal to a host computer that will be man managed.
3.3 Individual Block Design 3.3.1 Microcontroller
A microcontroller is used to handle the digital signal processing aspects of this project. Considering the fact that the intention is to limit the number of component items, the idea is then to eliminate the conventional signal generator used to provide signal of a preset frequency. Research uncovered a powerful and dynamic microcontroller with features that fit well with the design needs and dynamic enough to provide the carrier signal from the output of a 4MHz crystal oscillator. The ATmega32 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced Reduced Instruction Set Computer(RISC) architecture. By executing powerful instructions in a single clock cycle, the ATmega32 achieves throughputs approaching one Million Instruction Per Second(MIPS) per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to 10X faster than conventional Complex Instruction Set Computer(CISC) microcontrollers. The ATmega32 provides the following other features:
32Kbytes of In-System Programmable Flash Program memory with Read-While-Write capabilities
32 general purpose I/O lines
32 general purpose working registers
JTAG interface for Boundary-scan
On-chip Debugging support and programming
Three flexible timer/counters with compare modes, internal and external interrupts
Serial programmable USART.
The Idle mode stops the CPU while allowing the Universal Synchronous Asynchronous Receive and Transmit(USART), two-wire interface, A/D Converter, SRAM, timer/counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next external interrupt or hardware reset.. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega32 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications like this RFID reader design project, needed to demonstrate the improvement of access control with RFID technology.
3.3.2 RF Choke
This is designed to be a low-pass filter that knocks off the upper harmonics of the incoming 125kHz square wave signal, thereby turning the square wave signal into a 125kHz sine wave signal. This component block is designed similar to the conventional L-C low-pass filter. The design consideration for the choke was guided by the fact that the microcontroller provides a 125kHz signal with an amplitude of 5V. In other not to over work the microcontroller, a suitable R1 needs to be selected whose impedance is right enough to pass the current. Also to be considered is the fact that the value of the current needs to be high enough to drive the antenna. Hence due to its availability and little impedance size, an 82Ω resistor is expected to give us appreciable impedance. As depicted in the schematic, a 125kHz square wave is generated from a signal generator and passed on to the RF Choke. For the L-C low-pass filter with the output coming off the capacitor C2, the transfer function for low-pass filters, which is given in equation (3.1)
Figure 3.2 Design Schematic of our RF Choke
⁄
⁄√ But at resonance frequency of 125kHz
⁄
That is
Solving mathematically, equation 3.1 becomes:
from equation 3.4 by proper substitution and evaluation as follows:
(- c )
⁄ √
The expectation is that this capacitance will provide the needed gain for the filtering process.
3.3.3 Carrier Signal Amplifier
The signal is amplified before it is fed into the antenna coil. A complementary power amplifier circuit is typically used to boost the transmitting signal level. This design incorporates the power amplifier circuit design of Microchip®. Since the expected current level with respect to transmit power for the 125kHz signal lies between 0.66A and 0.8A, it is then expected that their amplifier circuit will fit into this design. With reference to figure 3.3, R2 and R3 act as voltage divider coupled with R4 to bias Q2. D1 and D2 are used in the half bridge to help reduce crossover distortion caused from differing points of either transistor Q1 or Q3 in the complementary push-pull amplifier circuit. R7 and R8 are temperature-compensation
"feedback" resistors in the emitter legs of the push-pull transistor circuit, compensating for the heat dissipation as a result of the diodes in series.
3.3.4 Reader Antenna Coil
An RF signal can be radiated effectively if the linear dimension of the antenna is comparable with the wavelength of the operating frequency. In an RFID application like this which is utilizing the LF (125kHz) band, the wavelength of the operating frequency is about 2.4km. Because of this long wavelength, a perfect antenna can never be formed in a limited space of the device. Alternatively, a small loop antenna coil that is resonating at the frequency of interest (i.e., 125 kHz) is used. This type of antenna utilizes near field magnetic induction coupling between transmitting and receiving antenna coils. The field strength falls off with r-3 (where r = distance from the antenna). This near field behaviour (r-3) is the main limiting factor of the read range in RFID applications.
Figure 3.3 Signal Amplifier Circuit
In RFID applications, the antenna coil is an element of resonant circuit and the read range of the device is greatly affected by the performance of the resonant circuit. The resonance frequency (fo) of the circuit is determined by:
√ where fo is the resonant frequency (in Hertz), L is inductance (in Henry) and C is capacitance (in Farads). The resonant circuit can be formed either series or parallel. The series resonant circuit has minimum impedance at the resonance frequency. As a result, maximum current is available in the circuit.
This series resonant circuit is typically used for the reader antenna. On the other hand, the parallel resonant circuit has maximum impedance at the resonance frequency, because it offers minimum current and maximum voltage at the resonance frequency. This parallel resonant circuit is used for the tag antenna.
The first consideration as adapted from H. Hardy (1976) for the antenna design is that the data rate for FSK(Frequency Shift Keying) signal is 12.5kHz, then a bandwidth of 25kHz is needed for a full data recovery. The quality factor ‘Q’ is then obtained from the relation:
⁄ But fo is 125kHz, so its easy to obtain Q as follows: ⁄
Also we can now obtain the inductance of our antenna from the relation:
⁄ With Q=5, r=82Ω and our resonance frequency remains the same, we obtain
L: ⁄
Which is approximately 0.5mH. To obtain the value of the coupling capacitor, we substitute the value of ‘L’ and the resonant frequency into equation (3.4), Firstly, we realise that
Then C
Then the value of the coupling capacitor to be in series with the inductor to make up the series resonant antenna is about 3.2nF. Since the C2 is grounded, the carrier signal (125 kHz) is filtered out to ground after passing the antenna coil. The circuit provides minimum impedance at the resonance frequency which results in maximizing the antenna current, and therefore, the magnetic field strength is maximized. In order to determine the coil parameters, we by optimisation with respect to the expected read range of our reader circuit obtain the gain of our antenna using equation (3.9) below as adapted from R. Gagliardi(1988):
√
Where λ=wavelength, Pt=power of transmitter, Gt=gain of transmitter, Gr=gain of tag and Pth is the tag response threshold. Knowing that the expected read range is about 0.1524m, λ is also known to be 2.4km, Pth is 0.16X10-6, Gr is 0.12dB, and Pt is 0.3mW, we can then compute the value for Gt: Firstly, we make Gt the subject of the formulae of equation (3.9) to obtain: ( ) equation 3.10 Now, substituting the already known values into equation (3.10)
( ) 0.16 10-6
( ) 2.83206X10-9dB.
Then the gain of the transmitter to be approximately equal to 2.83X10-9dB.
With this gain we can now employ the expression relating antenna gain and antenna width which is given as:
Where d is the width or diameter of antenna with regards to its nature:
rectangular loop or circular loop. Using the obtained gain, the antenna diameter can now be obtained as follows: From equation 3.11, we make d the subject of the formulae which is: √
Therefore √ - ( ) = 0.0360m
this is about 3.6cm. With this width and with a proportionate length, coupled with the value for inductance already obtained, we can now estimate our required number of coil turns for the antenna design using the expression shown in equation (3.12) below as adapted from F. Grover,(1946).
(( ) )
( ) Where L is the inductance (in milli-Henry), x and y are the width and length
of the coil (in cm), h is the height of the coil (in cm), b is the width across the
That is approximately 90 turns. Although these are estimates, fine tuning is expected during implementation.
3.3.5 Envelope Detection
The envelope detector is the first component of the receiver sub-system whose main task is to collect and process the modulated carrier wave in the electromagnetic field around the antenna. For the obvious fact that the transmitted wave is sent as an unguided wave, a receiving module must be used to convert the impinging field to an electronic waveform, which is then passed to the front end components for proper signal processing.
Although the transmitting antenna and receiving antenna are the same, it is also a task for the reader antenna to detect the amplitude variation of the tag and extract the modulation data. In this design a linear diode detector or peak detector is employed, which is a series connection of a diode and a capacitor outputting a DC voltage equal to the peak value of the applied AC voltage. The obvious reason for its utilization is that the peak diode detector uses the rectification property of a diode and maintains a linear relationship between the carrier amplitude and the detected output voltage. According to the schematic shown in figure 3.5, L1 is the receiving antenna coil; C1 is the resonant capacitor which makes sure that transmitted signals are not let through the receiving section. Diode D1 is a small signal fast recovery diode rectifier; it is a demodulator which detects the envelope of the backscattering signal. D1 and C2 form a half-wave capacitor-filtered rectifier circuit. The detected envelope signal is charged into the C2. R1 provides a
discharge path for the voltage charged in the C2. As is the norm for filtering AC signals in this manner there is some 125 KHz ripple, but choosing good values we could make the enveloping frequencies stand out from the ripple.
For this we chose R=390kΩ and C= 2.2nF, with respect to proven RC filter design from Microchip®. Once signal leaves this stage, it passes through the capacitor C3 to knock out the DC offset and into the next set of filters. Once signal leaves the envelope detector, it is passed through a capacitor to knock out the DC offset, before getting to the next stage of signal processing.
3.3.6 Filter and Amplifier
This stage of our device is required to pass the amplitude modulated band of frequencies, as modulated by the obtained RFID tags. Recalling that the modulation type used in the cards is Frequency Shift Keying (FSK), where the modulation is done by essentially multiplying a lower amplitude, lower frequency signal with the carrier signal, creating an AM-like effect; the lower
Figure 3.5 Envelope Detector Schematic
frequency enveloping the carrier frequency. To switch between a "1" and a
"0", the tag switches the modulating frequency. The two frequencies used by obtained cards are 12.5 KHz (125 KHz/10) and 15.625 KHz (125 KHz/8), which correspond to 1 and 0 respectively. Armed with this, it is expedient to design efficient filters to pass only a band of frequency carrying the data needed in the modulated signal. This act of band passage should also be accommodating of attenuation gain.
Using the Matlab Filter Design Tool, it is possible to fuse in expected specifications and parameters as regards the functionality of the filter. The figure shown in figure 3.6 is the filter builder dialog box that helps to design the filter needed. With the band pass parameters, the plot of magnitude against frequency showing gain paths is illustrated in figure 3.7.
Figure 3.6 Filter Design Dialog Box from Matlab
Having a response as depicted above, it is also possible to utilize the filter coefficients obtained from the Matlab Filter Design Tool to compute the transfer function from which the active and passive parameters of the filter could be obtained. But considering the large number of filter coefficients presented, it will be wise to search for an already designed filter with responses that resembles the above response. An almost perfect fit is the design presented on Discovercircuits.com by Jonathan Westhues. The bode plot of this design and circuit schematic are as shown below. This picked filter design comprise of a pair of active Twin-T filters and an active Butterworth filter with the TL084 Operational Amplifier as the gain element.
As can be seen from the Bode Plot, the first filter mostly isolate before the pass band (10-20 KHz), with roughly unity gain for all frequencies outside the
As can be seen from the Bode Plot, the first filter mostly isolate before the pass band (10-20 KHz), with roughly unity gain for all frequencies outside the