A.8.1
Single-Ended Line-Termination
[47] Recommends series termination for DDR designs with less than four DDR memory IC’s and trace lengths of less than 2 inches. Series termination dampens overshoot and simplifies PCB routing. Figure A.16 depicts series termination with a series resistor, RS, physically close to the FPGA for unidirectional signals and in the middle of the trace for bidirectional signals. Cis discarded for a bidirectional signal.
C RS VREF VOUT Z0 VREF VIN
Figure A.16: Series Termination Circuit
The values of RS and the trace impedance, Z0, are jointly chosen with a few considerations in mind. Firstly the availability of the chosen RSvalue, secondly the recommended trace width which is used in Appendix A.8.4 to calculate Z0and thirdly:
Z0= ROU T+ RS (A.8.1)
With the FPGA output-impedance:
ROU T = 25 Ω (A.8.2)
W = 0.1524 mm t = 0.035 mm h = 0.2 mm
The DDR memory operates with the Stub Series Terminated Logic for 2.5V (SSTL-2) Class II I/O standard. The following calculations are to check if the chosen RS and Z0values satisfy the relevant I/O specifications. The minimum DDR input high voltage is given as:
VIHmin= Vre f+ 0.15 V = 1.25 + 0.15 = 1.4 V (A.8.3)
The minimum FPGA output high voltage is given as:
VOHmin= Vre f+ 0.76 V = 1.25 + 0.76 = 2.01 V (A.8.4)
This means the minimum needed FPGA output high current is:
IOHmin=VOHmin−VIHmin
RS = 9.84 mA (A.8.5)
Which is less than the rated FPGA output high current of 16.4 mA. For communication in the opposite direction, the minimum FPGA input high voltage is given as:
VIHmin= Vre f+ 0.18 V = 1.25 + 0.18 = 1.43 V (A.8.6)
The minimum DDR output high voltage is given as:
VOHmin= Vre f+ 0.76 V = 1.25 + 0.42 = 1.67 V (A.8.7)
This means the minimum needed DDR output high current is:
IOHmin=
VOHmin−VIHmin
RS = 3.87 mA (A.8.8)
Which is much less than the rated DDR output high current of 16.8 mA. These results prove that the chosen RSand Z0values are compatible with the I/O standard in question.
A.8.2
Differential Line-Termination
[47] Recommends differential termination for the DDR CK and CK# traces with the termination resistor of between 100 Ω and 200 Ω. Figure A.17 depicts differential termination with series resistors, RS, physically close to the FPGA and a termination resistor, RT, physically close to the DDR.
The values of RS, RT and the trace impedance, Z0, are jointly chosen with a few considera- tions in mind. Firstly the availability of the chosen RS value, secondly the recommended trace width which is used in Appendix A.8.5 to calculate Z0and thirdly the differential clock signals example 5.4.1 in [48]. Z0is calculated as 100.3 Ω with:
W = 6 mil S = 7 mil
t = 1.378 mil B = 26.181 mil The series and termination resistors are thus chosen as:
RS Z0
RS Z0
RT
VSWING OUT VSWING IN
Figure A.17: Differential Termination Circuit
RS= 50 Ω (A.8.9)
RT = 100 Ω (A.8.10)
The DDR memory operates with the SSTL-2 Class II I/O standard. The following calcula- tions are to check if the chosen RS, RT and Z0values satisfy the relevant I/O specifications. The FPGA minimum output high and maximum output low voltages are given as:
V0Hmin= Vre f+ 0.76 V = 1.25 + 0.76 = 2.01 V (A.8.11)
V0Lmax= Vre f− 0.76 V = 1.25 − 0.76 = 0.49 V (A.8.12)
The minimum FPGA swing output voltage is thus calculated as:
VSW INGOU T min= V0Hmin−V0Lmax= 1.52 V (A.8.13)
The current through the termination network can be calculated as:
I=VSW INGOU T min
RS+ RT + RS
= 7.6 mA (A.8.14)
The minimum DDR input high voltage can now be calculated as:
VIHmin= V0Hmin− (I × RS) = 1.63 V (A.8.15)
Which is more than the minimum DDR rating of 1.6 V. The maximum DDR input low voltage can now be calculated as:
VILmax= V0Hmin− (I × (RS+ RT)) = 0.87 V (A.8.16)
Which is less than the maximum DDR rating of 0.9 V. These results prove that the chosen RS, RT and Z0values are compatible with the I/O standard in question.
A.8.3
PCB Layout Considerations
There are four aspects to consider when designing the high-speed PCB section connecting DDR memory to its controller, the FPGA. Firstly the orientation and distance of the DDR unit with respect to the FPGA. Secondly, trace length which has certain specifications. The third aspect is on which layer to route each trace type and the fourth is trace spacing. Trace thickness, on the other hand, is determined by the impedance calculations in Appendix A.8.1 and A.8.2 respectively.
The DDR signals are grouped into 3 sets, namely the Clock set, the Data/Data-strobe set and the Address/Command/Control set. Trace lengths and spacings are specified in [47]. It is also recommended to route the Data/Data-strobe set on an outer PCB layer, the Ad- dress/Command/Control set on the other outer PCB layer and the Clock set on an inner PCB layer. Figure A.18 shows the orientation of the DDR memory with respect to the FPGA which determines the maximum trace length. To stay within specifications for trace-length differences, the traces starting closer to the FPGA are lengthened by S-bends to optimizes the available space between the DDR and the FPGA. The last design technique to minimize cross-talk and noise, is to shield every signal layer with adjacent ground planes.
Figure A.18: DDR Orientation with respect to the FPGA
A.8.4
Single-Ended Trace Impedance Calculation
The trace impedance is calculated with an on-line microstrip transmission line characteristic impedance calculator [49]. This calculator uses the parameters shown in Figure A.19 where:
εr = Relative Dielectric Constant W = Width of trace
t = Thickness of trace h = Thickness of dielectric
r
Figure A.19: Impedance Calculation Parameters
The relative dielectric constant, εr, for FR41is 4.2. throughout the scope of this thesis. The calculator uses the following equations derived from [50], p94:
ForWh < 1:
Zo= √60 εeff × ln 8h W + W 4h (A.8.17) εeff = εr+ 1.0 2 + εr− 1.0 2 1 q 1 +12hW + 0.04 1 −W h 2 (A.8.18) Else : Zo = 120π√ εeff × W 1 h + 1.393 + 0.677 × ln W h + 1.444 (A.8.19) εeff = εr+ 1.0 2 + εr− 1.0 2 1 q 1 +12hW (A.8.20)
The trace impedance result calculated using this calculator coincides with the result when using CST Microwave Studio, a well known simulation package used in the field of Electro Magnetics.
A.8.5
Differential Trace Impedance Calculation
The differential trace impedance is calculated with the on-line Differential Stripline Impedance Calculator from IDEA Consulting [51]. This calculator uses the parameters shown in Fig- ure A.20 where:
εr = Relative Dielectric Constant W = Width of traces
S = Distance between traces t = Thickness of trace B = Thickness of dielectric
Figure A.20: Differential Impedance Calculation Parameters
The relative dielectric constant, εr, for FR42 is 4.2. throughout the scope of this thesis. The equations used by this calculator can be found in [50], p232-235, and are too extensive to include in this appendix.