There are three main requirements needed to design the SPM unit, namely: the type of input signals, what kind of output the unit produces, and the type of controller used inside the SPM.
Since SPM is used to control the power of the digital circuits, it has to have knowledge of previous power consumption in these circuits. Hence, one of the SPM inputs is the measured power of the system. This power signal is considered a feedback that tells the SPM whether the required reduction was achieved or not.
The environment that will host SPM is the multi standard digital communication system in which the change in the standard will change the used system clock frequency. If the frequency increases, then the power will increase as well, as was shown in section (3.4). The task of the SPM is to detect this frequency change and to choose an appropriate voltage to accomplish the required power reduction. Due to that, it is wise to either supply the frequency as an input to the SPM or give the SPM unit the knowledge about the used communication standard so that it can generate the required frequency to the communication system stages.
When the voltage of the digital system is reduced, the circuit time delay is increased. Since SPM will control the power of the digital circuit through voltages, there might be a case when the voltage supplied by the SPM increases the time delay to such an extent that the circuit cannot withstand the supplied voltage. If this happens, the SPM should increase the supplied voltage, which will decrease the time delay of the system. A signal that contains the current time delay of the circuit will let the SPM unit decide the best voltage for the Communication circuit.
An elementary configuration of the SPM unit inside the communication system is shown in Figure (4.1) where the system requirement is a signal that tells the SPM unit to generate the required stage clock frequency according to the used communication standard. The digital communication system shown in the Figure is designed using (Tang et al., 2012, 2013b)
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model. Each unit inside the digital communication system is responsible for a certain communication task such as Cyclic Redundancy Check (CRC), Turbo encoding, etc.
Figure (4.1): Digital Communication System with SPM Unit.
There are many types of controllers in control theory. Most of these controllers need a precise modelling for the system to be controlled so that an accurate controller is built based on the system model (Leonid, 1997). Looking at the digital system power model, it is obvious that it depends on random variables such as the architecture of the logic circuit and the number of inputs. Therefore, it is not possible to build a general classical controller for this system. Instead, the controller must look at the system model as a black box. Intelligent controllers like Fuzzy Logic Controllers (FLC) and Neural Network Controllers (NNC) are used in such systems (Lee, Vukovich, & Sasiadek, n.d.; Leonid, 1997; Murphy, 1992). NNC uses a lot of computation power and storage space, so it is not a good choice for power control. On the other hand, once the FLC is designed, it can be stored in a small ROM and used in the system. It consumes a small amount of energy and storage space (Tapou & Al-raweshidy, 2012; Tapou et al., 2011). Because of the previous discussion, SPM uses FLC to control the power in digital communication systems.
4.3.1. The Need for Coarse Control.
When Vdd is reduced, the circuit time delay will increase. In high frequencies, this can
lead to a miss pulse error in which the circuit will not be able to produce the correct output. The missed pulse occurs because the output gates will receive their inputs late and will not have the chance to produce the correct output due to their internal time delay. This effect is clearly shown
Unit 1 Unit2 Unit 3 Unit n
SPM Input Data Output Data System Requirements (V1,F1) (V2,F2) (V3,F3) (Vn,Fn) Digital Communication System (P1,Tmax1 ) (P2,Tmax2 ) (P3,Tmax3 ) (Pn,Tmaxn )
Chapter Four Smart Power Manager Unit Design
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in Figures (3.16), (3.19), (3.22), and (3.25) when the 2×1 MUX was tested under low voltage and very high frequency. This effect is reduced in two ways; either reducing the technology size or increasing the voltage and hence the power. The first solution is not applicable once the circuit is implemented which makes the second solution the best choice for such a problem.
If a miss pulse occurs, then the whole data are corrupted and that is a waste in power. So, the SPM should change its policy from reducing power consumption through reducing voltage, into reducing power consumption through saving data. This can only happen by increasing Vdd. A course controller was used to implement this task. The controller is simple; it
works under this algorithm 1. Measure Tmax.
2. If 𝐹 ≥ 1 𝑇
𝑚𝑎𝑥
⁄ then set Vdd to the maximum value.
3. If 𝐹 < 1 𝑇 𝑚𝑎𝑥
⁄ then use FLC to determine Vdd.
So if the input frequency is 10 MHz and the calculated Tmax corresponding to Vdd
produced by the FLC, is 16 ns, then the F is less than 1/Tmax or 10 MHz is less than 62.5 MHz.
and the used supply voltage is calculated using FLC. If the frequency is 200 MHz and Tmax
corresponding to Vdd is 16 ns, then the course controller should use the maximum voltage as a
supply voltage because 200 MHz is larger than 62.5 MHz. Such condition will ensure that the circuit time delay will not conflict with the used input frequency.