Development of Process Bus Lab Devices

The hardware implementation of process bus devices is achieved using hard-real time operating system, QNX platform [90] over the industrial embedded computer system. Moreover, the process bus communication network devices used for this investigation are commercially available, and designed for substation environment, from Ruggedcom [91].

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5.1.1

Merging unit simulator

Merging unit is implemented as a real time data playback using QNX. Figure 5-1 illustrates the real time data playback functional diagram. Various scenarios of a typical power system can be simulated using the PSCAD/EMTDC simulation tool to obtain signals of 3-phase to neutral currents and voltages using the COMTRADE recorder. Special file conversion code is developed using C/C++ programming, which converts 20 kHz COMTRADE data to the IEC 61850-9-2 compliant SV messages at 4800 Hz in a SV data file. This SV data file is sent to a real time data playback, working as a merging unit, in offline. With the help of the hard-real time timers of the operating system [90], the IEC 61850-9-2 compliant sampled value messages are sent to all subscribed protection IEDs over a process bus network at a regular interval (according to 4800 Hz sampling frequency). Moreover, this developed MU has capability to create various SV loss and delay scenarios over the IEC 61850-9-2 process bus, as well as to capture and read configured IEC 61850 GOOSE messages. The SV loss or delay applies to entire the sampled value packet, which includes voltages and currents obtained at the same time stamp from the corresponding CTs/VTs.

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5.1.2

Protection IED

Figure 5-2 shows the basic function block diagram of an implemented protection IED using industrial embedded systems with the real time operating system. The hard-real time operation of the protection IED is achieved with the help of various capabilities of the real time platform, such as, hard-real time timers, multi-threads, input/output packet (io-pkt), etc. To avoid complexity, the figure only illustrates the major function blocks related to digital relaying. It is desired that the SV estimation algorithm should work independent of a digital protection function. Therefore, functions related to SV capturing and buffering are grouped as independent process-1; and traditional protection functions (logical nodes as per IEC 61850) with GOOSE messaging are grouped as independent process-2. Real-time multi-threads are used to perform protection functions simultaneously with the SV packet buffering by executing both independent process threads in parallel. As the SV estimation algorithm is implemented as a part of SV buffer, it is independent of protection functions. This way, SV estimation can be implemented in an IED to work with any traditional digital relaying algorithm. Although, the SV estimation algorithm is simple and easy to implement in digital protection IEDs, it will require additional processing.

As illustrated in Figure 5-2, IEC 61850-9-2 enabled protection IED receives and filters

various types of messages from Ethernet network port. SV data dissect function is

developed to read voltage and current values from the standard IEC 61850-9-2 packet format; as well as to store these values in a circular SV buffer. The sampled value buffer is filled in sequence. The delayed or lost sampled value packets will be estimated using the proposed SV estimation algorithm, as explained in Appendix. The protection IED also has capability to configure, encapsulate and multicast the IEC 61850-8-1 GOOSE messages to the subscribed MUs and other IEDs.

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Figure 5-2 Function block diagram of the IEC 61850-9-2 enabled protection IED developed in a laboratory

5.1.3

Implementation of the SV estimation algorithm

The implementation of a first order SV estimation technique is discussed in this appendix to avoid complexity. Figure 5-3 shows the flow diagram of the SV estimation algorithm for the IEC 61850-9-2 enabled protection IED.

The digital values of voltage and current signals obtained from the SV packet are stored in the Sampled Value Buffer (SVB), as shown in Figure 5-2. To store received sampled values in sequence and to detect sample value loss in SVB, the sampled value estimation

algorithm uses two pointers: 1) sampled value buffer pointer (SVB_ptr); and 2) previous

sampled value buffer pointer (SVB_ptr_prev). The value of SVB_ptr would be the same

as the value of Sample Count data field defined in IEC 61850-9-2 standard. If the

received sampled value is the delayed one, the previously estimated sampled value is

replaced by this received actual value in the SVB. In case, if difference between SVB_ptr

and SVB_ptr_prev is higher than maximum count, this condition will initiate ALARM without estimating sampled values and this may be due to loss of communication link. If

77 the lost/delayed SV packets are less than the maximum count, which implies that there is SV loss or delay, and therefore, the algorithm selects coefficients as well as estimates the lost sampled values. Further details can be obtained from reference [92].

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5.1.4

Traffic generator

A traffic generator is implemented to generate different types of IEC 61850 traffic within the Virtual LAN (VLAN) of a particular protection system using the real time platform. In this work, the traffic streams used over the process bus are GOOSE, GSSE (Generic Substation Status Event), and client server applications. The traffic configuration with total traffic in Mbps is listed in Table 5-1.

Table 5-1 Traffic generator configuration Sr. No. Types of Messages Ethernet Interfaces Packet size (byte) Inter- arrival time Total Traffic (Mbps) 1 GOOSE 2 162 500 µsec 5.184 2 GSSE 2 281 1 msec 4.49 3 Client/server applications 2 1456 1 msec 23.296 Total 32.97

5.1.5

Network analyzer

WireShark software is used as a network analyzer in a windows PC [93]. The network analyzer is configured in promiscuous mode to sniff all the packets from the entire IEC 61850-9-2 process bus network. It captures all the data packets from the network, and displays the content/structure of a packet in detail. In this hardware set-up, network analyzer is used to confirm the number of lost or delayed SVs, as well as to analyze the total traffic on the process bus.