Advanced high frequency bipolar devices fabricated in BiCMOS technology are built by adding a minimum number of compatible process steps to a standard RF CMOS process flow.
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The classic silicon bipolar fabrication approach of ion-implantation and annealing is not compatible with RF CMOS processing flows due to the high temperatures required during anneal. Also, implant/anneal techniques cannot provide the control needed for extremely thin, highly doped intrinsic base layers. Higher frequency bipolar devices require epitaxial growth and in-situ doping methods. Epitaxy growth and doping techniques by low temperature methods, at around 500 oC, make it possible for SiGe HBT’s and CMOS to be compatible in a single technology [21],[19]. The full process cross-section of the SiGe HBT modeled includes: first level aluminum metallization, tungsten (W) interconnect plugs and P+ substrate access is shown in Figure 5.1.
Figure 5.1 Cross-section indicating P- substrate surface contact and deep trench device
isolation[25],[9].
Device-to-device isolation is obtained by a deep trench surrounding the transistor. The poly filled deep trench go beyond the depth of the N+ buried collector and terminates well into the P-
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substrate. Thus the device is sidewalled isolated and junction isolated on the bottom. Surface contact to the P- substrate is made by a deep P+ plug implant, as shown in the full transistor cross-section of Figure 5.1. The high temperature P+ implant and annealing process steps occur prior to the lower temperature process steps in the fabrication flow [28]. The P+ access to the substrate layer is not included in the standard layout of the transistor. The designer has complete freedom to place a P- substrate contact any distance from the device structure [7]. Therefore, the model development of the SiGe HBT for the P- substrate stops at the P- layer within the material.
The SiGe HBT has a minimum feature size, polysilicon doped emitter of 0.5µm x 2.5µm [7]. The electrical regions are overlaid onto a cross-section of the intrinsic transistor in Figure 5.2. The heavy doping ability of polysilicon type emitters reduces emitter resistance. Surface contact to the intrinsic base is through the extrinsic P+ polysilicon base region extending from the intrinsic base on all four sides, thereby reducing the base resistance. The 4-sided P+ polysilicon extrinsic base region has a complete silicided contact that is accessed by metallization on one side of the emitter. The extrinsic base region sets above shallow trench isolation thereby, reducing base-collector capacitance.
In general, high frequency response bipolar devices must have a heavily doped, thin, intrinsic base width and a lightly doped collector width. Epitaxial growth techniques provide precise control of layer thickness and heavy doping ability.
The active areas of the SiGe HBT are formed by in situ doped epitaxial growth methods. The doping profile [21] of the modeled SiGe HBT in Figure 5.3 indicates the intrinsic layer thicknesses and charge concentrations of the device structure. The process information of the modeled SiGe HBT cross-section drawn above has been summarized in Table 5.1.
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Figure 5.2 SiGe HBT intrinsic transistor cross-section. Electrical regions indicated. 0.5µm x 2.5µm emitter SiGe HBT
Active Region
Width (nm)
Dopant, Concentration Bandgap (cm-3) Difference Emitter Epi-layer WE = 40 As NdE = 5·1020 to 1.5·1019
Intrinsic Base Epi-layer WB = 80 B+ NaB = 5·1018 ΔEg,Ge(grade)=37.5meV Trapezoidal Ge% profile 8% to 3% Epi-Layer Collector Wepi =380 P- Nepi = 4·1016 to 2 ·1017
Buried Layer Collector Wburied =150 As Nburied = 1018 to 2·1019
Table 5.1 Intrinsic region widths and dopant concentrations of modeled SiGe HBT [21]
The difference between the SiGe HBT and silicon high frequency bipolar structure occurs in the very thin epitaxial base region. The SiGe HBT is a SiGe alloy and not silicon. The SiGe HBT’s epi-base layer is grown on top of the thicker Si lightly doped collector epitaxial layer of approximately 400nm.
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Figure 5.3 Intrinsic HBT impurity profile vs. depth with the Ge% trapezoid profile within the base region indicated [21]. Note: Ge% is defined on a linear scale by the right-side vertical axis. The dotted line indicates the interface between the polysilicon emitter and Si epitaxial emitter region.
At the interface of the N- epi-layer collector and P+ base epi-layer, a high concentration of germanium (Ge%) is introduced. The Ge% is then linearly reduced as the base epi-layer is grown with a high P+ doping concentration. The inclusion of a Ge% concentration is abruptly stopped at the P+ base interface to the N+ emitter epilayer, thereby forming a trapezoidal Ge% profile in the intrinsic base. The trapezoidal Ge% profile of the modeled SiGe HBT is included in the doping profile [21] of Figure 5.3. This profile is from the classic Meyerson & Harame paper [21] which describes the Ge% profile gradient ranging from 8% to 3% across the base. A bandgap
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difference, ΔEg,Ge(grade), of approximately 37.5 meV would be expected by applying the graded Ge% concentration base analysis of section 2.3 and the design figure of merit that 10% Ge concentration produces a bandgap difference of 75 meV [21]. The SiGe base epi-layer is grown to a precise depth for two reasons. First, an exact trapezoidal shaped Ge% profile is required across the intrinsic base layer. Second, the stress increases as the SiGe layer thickness increases. The SiGe epitaxial base is being compressed as it is grown onto the Si epitaxial collector layer. However, very thin epilayers are able to maintain the stress stability of the pseudomorphic growth of a SiGe alloy layer. The modeled process has a SiGe alloy layer of approximately 80nm in depth.
The SiGe alloy layer requires a very thin Si buffer layer be grown on top. The buffer layer maintains the strained lattice structure of the alloy. This thin epilayer also becomes the emitter region. A polysilicon emitter is formed on the thin Si emitter buffer layer. The Si buffer emitter layer receives a high N+ doping concentration during the poly-emitter implant. The Si emitter layer is approximately 40nm thick.
The Mextram model makes use of the device regions and processing information for model topology and initial parameter values. Doping concentrations correspond to mobility which is used to determine temperature coefficient parameters. The epilayer parameters are initially calculated from the N- epi-collector doping and thickness.