Diffusion-rounded CMOS for improving both I on and I off characteristics

As semiconductor industries move to aggressive scaling to reduce the area and dynamic power consumption, the channel length has become as short as a few nanometers [17]. Thus imperfect patterning becomes significant not only in the poly gate channel shape but also in the diffusion profile. Many researches have been conducted to model and analyze the transistors’ profile in terms of driving current (Ion) and leakage current (Ioff) for post-lithographic simulations [7, 8, 23, 43]. In this work, we propose a novel layout approach to achieve a better driving capability and better leakage property by using imperfect diffusion rounding patterning. TCAD simulations. Analysis have shown that Ion and Ioff characteristics behave differently depending on whether diffusion rounding occurs at the source side or at the drain side of the transistor. Both Ion and Ioff properties become positive when the diffusion rounding happens at the source side. Therefore, the optimized layout provides enhanced device performance, and leakage power saving is made possible simultaneously. In other words, we propose a diffusion-rounded CMOS layout to exploit this positive effect of diffusion rounding at the transistor source side. This work is organized as follows; Chapter 3.2.1 explains electrical properties of diffusion rounding effect in detail, Chapter 3.2.2 investigates the proposed diffusion-rounded CMOS in delay and standby power. Chapter 3.2.3 analyzes several logic families to validate how much benefit we can achieve by employing the proposed diffusion-rounded CMOS. In Chapter 3.2.4, the layout issue of the proposed method is presented, and Chapter 3.2.5 concludes this work.

This work presents a simple and optimized device layout developed by using diffusion rounding effect for better electrical behavior of transistors. TCAD analysis shows that diffusion rounding at the transistor source side can provide increased Ion with decreased Ioff because of the edge effect. The

proposed diffusion-rounded CMOS shows as much as 10% improvement in the on-current (driving) and the off-current (leakage) is saved up to 10%. The inverter layout shows that proposed method requires less than a 4% cell area increase for the same driving strength of original cells.

3.2.1 Diffusion rounding effect

To quantify the benefit of diffusion rounding in the electrical characteristics of transistors, TCAD simulations of 45-nm bulk CMOS are conducted. The parameters of nominal devices are calibrated to match the 45-nm predictive models [66]. Table 3-3 lists the Ion and Ioff comparison between nominal devices and diffusion-rounded devices. The source side diffusion rounding shows better property both in Ion and Ioff. In other words, the driving current increases and the leakage current decreases at the same time when the source side diffusion shape rounded. Therefore, we can generate an optimized layout to achieve better Ion/Ioff characteristics by shaping the rounding in the source side. In the conventional CMOS layout, the source side active area is connected to the power supply; VDD for PMOS and GND for NMOS. And the diffusion rounding size depends not only on the manufacturing process but also on

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the layout rules such as the gate channel line end extension (LEE) and distance between the gate poly and the active area bending. In the gpdk45 nm [67] layout, the design rule of the minimum distance from the poly edge to the diffusion is 50 nm. And the width of the active area (either source or drain) is 140 nm. Therefore, 90 nm width and 45 nm height bending shape to form diffusion rounding can be easily applied.

3.2.2 Electrical properties of diffusion-rounded MOSFET

To introduce diffusion rounding in the source side to improve both Ion and Ioff, a 45-nm active area

protrusion is chosen at both sides of the source area. The Sentaurus TCAD setup of NMOS/PMOS is calibrated to the SPICE Ion/Ioff data in 45-nm BPTM [8]. After calibration, the diffusion-rounded NMOS

and PMOS are generated by using analytical models which are proposed in [4]. We applied the models by changing width of the transistors for Ion and Ioff to include the diffusion rounding effects. Figure 3-13

shows the proposed layout for NMOS. Table 3-3 shows that a 45-nm diffusion rounding at the source side can increase 10% of driving current (Ion), saving up to 10% leakage current (Ioff). These

observations led us to conclude that having diffusion rounding at the source side improves both Ion and

Ioff characteristics of the transistors. The effective channel width for the diffusion-rounded device is

longer than that of the original device. Therefore, the driving current of the diffusion rounded transistors is greater than that of the original, non-diffusion-rounded transistors [8, 43]. The Vth of the device is not

Table 3-3. TCAD simulation results showing the effect of diffusion rounding.

Length (nm) TCAD Normalized

NMOS source drain Ion (µA) Ioff (nA) Ion Ioff

rectangular 155 155 161.73 72.56 1.00 1.00

source + 45nm 200 155 180.87 68.99 1.12 0.95

source + 90nm 245 155 199.15 65.57 1.23 0.90

drain + 45nm 155 200 175.80 77.61 1.09 1.07

drain + 90nm 155 245 188.91 81.92 1.17 1.13

PMOS source drain Ion (µA) Ioff (nA) Ion Ioff

rectangular 300 300 184.31 67.18 1.00 1.00

source + 45nm 345 300 194.40 63.85 1.05 0.95

source + 90nm 390 300 204.64 61.92 1.11 0.92

drain + 45nm 300 345 192.66 68.15 1.05 1.01

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uniform along the channel width, but the Vth at the edge of the device is much smaller than that at the

center [8]. The effective channel length at the edge of the device is longer for a diffusion-rounded device than that of the original device without diffusion rounding. Therefore, the diffusion-rounded CMOS shows less Ioff than the original nominal devices. E-field and current density analysis of TCAD also

indicate reduced Ioff and increased Ion when we form rounding shape at the source side of the transistors.

So it is confirmed that source side diffusion rounding provides higher driving current due the effective channel increment, at the same time, and lower leakage current due to the reduced edge effect and E- field.

3.2.3 Simulation results

Using the analytical diffusion rounding models proposed in [43], we generate the diffusion-rounded NMOS and PMOS by changing effective Vth, effective width, and channel length. And HSPICE

simulations are conducted for several CMOS logic gates such as the inverter, NAND2, and NOR2 to measure the benefits of diffusion rounding. To investigate circuit level implication of diffusion rounding benefits, the 101-stage ring-oscillators and FO4 delay metrics are used. Figure 3-12 shows the inverter propagation delay result of original CMOS and diffusion-rounded CMOS. The diffusion-rounded

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CMOS inverter represents up to 13% speed up greater than the original CMOS inverter with 50 fF load capacitance. Power simulation shows that the leakage power of the original CMOS is 142 nW and that of the diffusion-rounded CMOS is 127 nW, which is nearly 10% smaller than the original CMOS inverter leakage power.

3.2.4 Layout perspective

To form diffusion-rounded transistors for PMOS and NMOS, the active area layout and thus mask design are modified and the overall cell layout is increased to meet the design rules. Several gate layouts (i.e., INV, NAND2, NOR2) are generated and compared to assess the layout tradeoff by improving electrical property in diffusion-rounded CMOS. The cadence generic 45 nm design package and the layout rules are used for the layouts [67]. Figure 3-13 shows the inverter layout comparison between the original and the diffusion-rounded CMOS. (a) shows the original layout of conventional CMOS and the proposed diffusion rounded one and (b) represents the printed images with OPC in Calibre Workbench [65] simulations. We used the minimum space for all the layers in the GPDK45nm design rule [67]. The minimum distance between the poly edge and the diffusion is 50nm. The 90nm width and 45nm height bending shape is inserted to form the rounding at the source side diffusion. As shown in Figure 3-13(b), the rounding shape at the source side appears with the 193nm wavelength optical lithography. The cell height increases from 1.07 µm to 1.19 µm, which is about 11% in the diffusion- rounded CMOS layout, but we have a better driving strength in the diffusion-rounded CMOS. Therefore,

(a) (b)

Figure 3-13. Inverter layouts of both original and diffusion rounded CMOS; (a) shows layouts and (b) shows the printed image with OPC. Note, black circles indicated the source side bending shape to form diffusion rounding.

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we can match the same driving strength by using a smaller channel width in the diffusion-rounded CMOS gates. For the same driving strength, the diffusion-rounded CMOS cell height increases only 50nm that results in less than a 4% cell area increase compared to the conventional CMOS. In addition, as the gate width increases and the logic gates become complicated, the area penalty to form the diffusion rounding shape in the source sides will be minimal. As the minimum feature size of the chip becomes small, the cost for mask generation increases to apply intensive RET techniques including OPC. Thus the complexity and controllability of the proposed design layout might be worse. However, we can apply the proposed diffusion-rounded logics in minimal area where we require either faster transistors to improve overall speed and/or less leaky gates to reduce standby power for specific blocks.

3.2.5 Chapter summary

In this work, we propose a simple layout method to boost the driving strength of logic gates and also to save the leakage power with a minimal area overhead. The proposed method provides up to 13% speed up and also saves up to 10% leakage current in an inverter simulation by exploiting the diffusion rounding phenomena in the transistors. The layout of the diffusion rounded CMOS shows a minimal impact in the cell area compared to the original compact layout. To verify the feasibility and benefit of the diffusion rounding effect on the real wafer, further research and simulations are necessary on the layouts of transistors with different diffusion rounding size and locations.

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Chapter 4.

Optimization and analysis of process-induced trapezoidal fin