• •
01110 = Reserved. No channel connected.
01101 = AN13 01100 = AN12 01011 = AN11 01010 = AN10 01001 = AN9 01000 = AN8 00111 = AN7(4) 00110 = AN6(4) 00101 = AN5(4) 00100 = AN4 00011 = AN3 00010 = AN2 00001 = AN1 00000 = AN0
bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note 1: See Section 17.0 “Digital-to-Analog Converter (DAC) Module” for more information.
2: See Section 14.0 “Fixed Voltage Reference (FVR)” for more information.
3: See Section 16.0 “Temperature Indicator Module” for more information.
4: Not available on the PIC16(L)F1933/1936/1938.
PIC16(L)F1938/9
REGISTER 15-2: ADCON1: A/D CONTROL REGISTER 1
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
ADFM ADCS<2:0> — ADNREF ADPREF<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is loaded.
0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is loaded.
bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits
111 = FRC (clock supplied from a dedicated RC oscillator) 110 = FOSC/64
101 = FOSC/16 100 = FOSC/4
011 = FRC (clock supplied from a dedicated RC oscillator) 010 = FOSC/32
001 = FOSC/8 000 = FOSC/2
bit 3 Unimplemented: Read as ‘0’
bit 2 ADNREF: A/D Negative Voltage Reference Configuration bit 1 = VREF- is connected to external VREF- pin(1)
0 = VREF- is connected to VSS
bit 1-0 ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits
11 = VREF+ is connected to internal Fixed Voltage Reference (FVR) module(1) 10 = VREF+ is connected to external VREF+ pin(1)
01 = Reserved
00 = VREF+ is connected to VDD
Note 1: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See the applicable Electrical Specifications Chapter for details.
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REGISTER 15-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<9:2>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result
REGISTER 15-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<1:0> — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 ADRES<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use.
PIC16(L)F1938/9
REGISTER 15-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — — — — — ADRES<9:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-2 Reserved: Do not use.
bit 1-0 ADRES<9:8>: ADC Result Register bits Upper two bits of 10-bit conversion result
REGISTER 15-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ADRES<7:0>: ADC Result Register bits Lower eight bits of 10-bit conversion result
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15.4 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 15-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 15-4. The maximum recommended impedance for analog sources is 10 k. As the
source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 15-1 may be used. This equation assumes that 1/2 LSb error is used (1,024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution.
EQUATION 15-1: ACQUISITION TIME EXAMPLE
TACQ = Amplifier Settling Time +Hold Capacitor Charging Time+Temperature Coefficient = TAMP+TC+TCOFF
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
The value for TC can be approximated with the following equations:
Solving for TC:
Therefore:
Temperature = 50°C and external impedance of 10k 5.0V VDD
Assumptions:
Note: Where n = number of bits of the ADC.
TACQ = 2µs+1.20µs+50°C- 25°C0.05µs/°C = 4.45µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.
PIC16(L)F1938/9
FIGURE 15-4: ANALOG INPUT MODEL
FIGURE 15-5: ADC TRANSFER FUNCTION
CPIN
= Leakage current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance
various junctions
RSS
Note 1: Refer to in the applicable Electrical Specifications Chapter.
RSS = Resistance of Sampling Switch Input
VREF- Zero-Scale
Transition
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TABLE 15-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register on Page
ADCON0 — CHS<4:0> GO/DONE ADON 155
ADCON1 ADFM ADCS<2:0> — ADNREF ADPREF<1:0> 156
ADRESH A/D Result Register High 157
ADRESL A/D Result Register Low 157
ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 126
ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 131
ANSELE — — — — — ANSE2 ANSE1 ANSE0 141
CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 228
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 91
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 94
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 125
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 130
TRISE — — — — —(2) TRISE2(1) TRISE1(1) TRISE0(1) 140
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 148
DACCON0 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 168
DACCON1 — — — DACR<4:0> 168
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not used for ADC module.
Note 1: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’.
2: Unimplemented, read as ‘1’.
PIC16(L)F1938/9
NOTES:
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16.0 TEMPERATURE INDICATOR MODULE
This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC.
The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A one-point calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, “Use and Calibration of the Internal Temperature Indicator” (DS01333) for more details regarding the calibration process.
16.1 Circuit Operation
Figure 16-1 shows a simplified block diagram of the temperature circuit. The proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions.
Equation 16-1 describes the output characteristics of the temperature indicator.
EQUATION 16-1: VOUT RANGES
The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See Section 14.0 “Fixed Voltage Reference (FVR)” for more information.
The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no current.
The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the FVRCON register, provides a wider output voltage. This provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher VDD is needed.
The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation.
FIGURE 16-1: TEMPERATURE CIRCUIT DIAGRAM
16.2 Minimum Operating V
DDWhen the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications.
When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high enough to ensure that the temperature circuit is correctly biased.
Table 16-1 shows the recommended minimum VDD vs.
range setting.
TABLE 16-1: RECOMMENDED VDD VS.
RANGE
16.3 Temperature Output
The output of the circuit is measured using the internal Analog-to-Digital Converter. A channel is reserved for the temperature circuit output. Refer to Section 15.0
“Analog-to-Digital Converter (ADC) Module” for detailed information.
16.4 ADC Acquisition Time
To ensure accurate temperature measurements, the user must wait at least 200s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200s between sequential conversions of the temperature indicator output.
High Range: VOUT = VDD - 4VT
PIC16(L)F1938/9
TABLE 16-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on page
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR<1:0> 118
Legend: Shaded cells are unused by the temperature indicator module.
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17.0 DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels.
The input of the DAC can be connected to:
• External VREF pins
• VDD supply voltage
• FVR (Fixed Voltage Reference)
The output of the DAC can be configured to supply a reference voltage to the following:
• Comparator positive input
• ADC input channel
• DACOUT pin
• Capacitive Sensing module (CPS)
The Digital-to-Analog Converter (DAC) can be enabled by setting the DACEN bit of the DACCON0 register.
17.1 Output Voltage Selection
The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register.
The DAC output voltage is determined by the following equations:
EQUATION 17-1: DAC OUTPUT VOLTAGE
17.2 Ratiometric Output Level
The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value.
The value of the individual resistors within the ladder can be found in Section 30.0 “Electrical Specifications”.
17.3 DAC Voltage Reference Output
The DAC can be output to the DACOUT pin by setting the DACOE bit of the DACCON0 register to ‘1’.
Selecting the DAC reference voltage for output on the DACOUT pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin. Reading the DACOUT pin when it has been configured for DAC reference voltage output will always return a ‘0’.
Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for external connections to DACOUT. Figure 17-2 shows an example buffering technique.
IF DACEN = 1
PIC16(L)F1938/9
FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
32-to-1 MUX
DACR<4:0>
R
VREF -DACNSS
R R R
R
R R
32 DAC Output
DACOUT 5
(to Comparator ADC modules)
DACOE VDD
VREF+
DACPSS<1:0> 2 DACEN
Steps
Digital-to-Analog Converter (DAC)
FVR BUFFER2
R
V
SOURCE-VSOURCE+
VSS DACLPS
and
DACOUT + Buffered DAC Output
– DAC
Module
Voltage Reference
Output Impedance
R PIC® MCU
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17.4 Low-Power Voltage State
In order for the DAC module to consume the least amount of power, one of the two voltage reference input sources to the resistor ladder must be disconnected.
Either the positive voltage source, (VSOURCE+), or the negative voltage source, (VSOURCE-) can be disabled.
The negative voltage source is disabled by setting the DACLPS bit in the DACCON0 register. Clearing the DACLPS bit in the DACCON0 register disables the positive voltage source.
17.4.1 OUTPUT CLAMPED TO POSITIVE VOLTAGE SOURCE
The DAC output voltage can be set to VSOURCE+ with the least amount of power consumption by performing the following:
• Clearing the DACEN bit in the DACCON0 register.
• Setting the DACLPS bit in the DACCON0 register.
• Configuring the DACPSS bits to the proper positive source.
• Configuring the DACR<4:0> bits to ‘11111’ in the DACCON1 register.
This is also the method used to output the voltage level from the FVR to an output pin. See Section 17.5
“Operation During Sleep” for more information.
Reference Figure 17-3 for output clamping examples.
17.4.2 OUTPUT CLAMPED TO NEGATIVE VOLTAGE SOURCE
The DAC output voltage can be set to VSOURCE- with the least amount of power consumption by performing the following:
• Clearing the DACEN bit in the DACCON0 register.
• Clearing the DACLPS bit in the DACCON0 register.
• Configuring the DACNSS bits to the proper negative source.
• Configuring the DACR<4:0> bits to ‘00000’ in the DACCON1 register.
This allows the comparator to detect a zero-crossing while not consuming additional current through the DAC module.
Reference Figure 17-3 for output clamping examples.
FIGURE 17-3: OUTPUT VOLTAGE CLAMPING EXAMPLES
17.5 Operation During Sleep
When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled.
17.6 Effects of a Reset
A device Reset affects the following:
• DAC is disabled.
• DAC output voltage is removed from the DACOUT pin.
• The DACR<4:0> range select bits are cleared.
R
-Output Clamped to Positive Voltage Source Output Clamped to Negative Voltage Source
PIC16(L)F1938/9
17.7 Register Definitions: DAC Control
TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE REGISTER 17-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0
R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0
DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 DACEN: DAC Enable bit 1 = DAC is enabled 0 = DAC is disabled
bit 6 DACLPS: DAC Low-Power Voltage State Select bit 1 = DAC Positive reference source selected 0 = DAC Negative reference source selected bit 5 DACOE: DAC Voltage Output Enable bit
1 = DAC voltage level is also an output on the DACOUT pin 0 = DAC voltage level is disconnected from the DACOUT pin bit 4 Unimplemented: Read as ‘0’
bit 3-2 DACPSS<1:0>: DAC Positive Source Select bits 11 = Reserved, do not use
10 = FVR Buffer2 output 01 = VREF+ pin 00 = VDD
bit 1 Unimplemented: Read as ‘0’
bit 0 DACNSS: DAC Negative Source Select bits 1 = VREF
-0 = VSS
REGISTER 17-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1
U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — DACR<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 DACR<4:0>: DAC Voltage Output Select bits
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on page
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 148
DACCON0 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 168
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