10 Combinational logic
10.1 Digital logic basics
4 W resistors, two VP0610L and two VN0610L MOSFET transistors, three 2N3904 transistors, three diodes, one LED, one red LED (optional), 74HC00, 7432, 7485, 7486 TTL or TTL-compatible logic chips, logic switches, and logic displays.
10.1 Digital logic basics
In this section we introduce the 7400 series of CMOS and TTL digital-logic chips. Unlike the analog ICs you’ve used up to now, which can output any voltage within some range determined by the power-supply voltages, digital-logic ICs employ only two ranges of output voltages, referred to as logic levels, about which more below. These levels can be used to represent true or false logical conditions or the zero and one of binary arithmetic.
The 7400 series is not the only logic series, nor are CMOS and TTL the only types of logic circuitry; however, they are the most commonly used. Other logic families include the CMOS 4000 series and the ECL
125
(emitter-coupled logic) 10 000 and 100 000 series. Each logic family has its own logic levels, speed, and recommended supply voltages.
The integrated circuits you will be using now are much more specialized than the general-purpose 741 op amp and 555 timer. They feature much higher bandwidth, with typical transition speeds of order volts/nanosecond (in contrast to the volts/microsecond slew rate of the 741). While greater complexity often means higher cost, the basic chips in the 7400 families (such as the 74HC00, 74LS00, and 74ACT00) cost less than $0.50 each in small quantities, with the more complex chips ranging toward several dollars.
10.1.1 Logic levels
Digital chips employ two voltages to represent two possible states. These voltages are called logic levels and can be used to represent the two states of Boolean algebra1 as well as the two digits of binary arithmetic. There are three ways of referring to logic levels:
r true and false, r zero and one, and r high and low.
In TTL logic, a voltage exceeding+2 V is called high, while a voltage less than+0.8 V is called low. To ensure noise margin, TTL outputs are guaranteed to put out at least+2.5 V in the high state and at most +0.4 V in the low state (see Fig. 10.1). This means that, even in the presence of up to 400 mV of noise, an output low will be recognized as low by the input of the next logic circuit, and similarly for high. The comparable CMOS levels are+3.5 and +1.5 V for the inputs and +4.5 and +0.5 V for the outputs.
While TTL chips are always powered from a+5 V supply, many CMOS chips are tolerant of supply voltages ranging from+2 to +6 V. It is therefore convenient to reference CMOS logic levels to the power-supply voltage VCC. The minimum input voltage interpreted as a CMOS high (VIH) equals 0.7 × VCC, while the maximum input voltage interpreted as a CMOS low (VIL) equals 0.3 × VCC. The output voltages VOHand VOL will vary with supply voltage as well.
The ‘high/low’ nomenclature is unambiguous, since it directly charac-terizes voltages, but the other two nomenclatures rely on a convention,
1 Also known as symbolic logic.
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Fig. 10.1. Logic levels for various 7400-family lines. VCCis the most positive voltage; VIL
and VIHare the maximum input low and minimum input high voltages.
which can be assigned either of two ways. The more common convention is positive logic: high=1=true, low=0=false. But there are occasionally situations in which it is more convenient to employ negative logic, in which high=0=false and low=1=true. (Another way to think about logic circuits is in terms of assertion-level logic, which is a hybrid of positive and negative logic that we will introduce in the next chapter.)
10.1.2 Logic families and history
As indicated in Table 10.1, CMOS and TTL chips come in a plethora of types, each with its own speed, power dissipation, input load, and output-current characteristics. This reflects the historical development of the var-ious series. Since our initial purpose is to become familiar with the logic, the details of speed and power are (for now) unimportant, but you will need a general familiarity with them so as not to be in the dark when you encounter them in future. Also there are restrictions on fanout (the number of inputs that an output can drive) which matter when actually designing circuits. For example, one LS-TTL output can drive twenty LS-TTL inputs, but only four S-TTL inputs. In what follows we use ‘7400’ generically to
Table 10.1. Common families within the 7400 series.
Family Year Brief description
TTL 1968 bipolar transistor–transistor logic
S 1974 TTL with Schottky transistors
LS 1976 low-power Schottky TTL
ALS 1979 advanced low-power Schottky
F 1983 fast TTL
HC 1975 high-speed CMOS
HCT 1975 high-speed CMOS (TTL compatible)
AC 1985 advanced CMOS
ACT 1985 advanced CMOS (TTL compatible)
LVC 1993 low-voltage CMOS
AHC 1996 advanced high-speed CMOS
refer to chips from any of these families. Unless otherwise specified, the chip families you actually use will depend on what happens to be on hand in the laboratory or (if you are working through this book on your own) on what you happen to find available.
Part numbers
The original TTL chips were the 7400 series and the corresponding ‘Mil Spec’ (military specification) 5400 series; these became popular in the 1970s. TTL chips are labeled with part numbers that begin with a letter code (such as ‘SN’) that is typically different for each manufacturer (see Fig. 10.2); then comes the ‘74’ that identifies the device as belonging to the 7400 series; then there may be a letter code that identifies the family; then the number that identifies the particular device (e.g. 00 for a quad NAND gate, 01 for quad NAND with open-collector outputs, 02 for quad NOR gate, 74 for dual D-type flip-flop, etc.); and finally there may be letters that indicate package style, reliability, degree of testing by the manufacturer, etc. (For example, the MC74LS00ND is a Motorola LS-TTL quad NAND gate in the plastic dual-in-line package with 160 hour ‘burn-in’ testing.) Pinouts and data sheets
Data sheets are available on the web or in data books produced by the chip manufacturer. The sheets specify the function of each pin of the IC package and provide detailed data on chip performance. In general, 7400-series chips have compatible pinouts independent of the family. For example, the
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Fig. 10.2. Labeling of 7400-series chips.
pinout for a 74HC00 quad NAND IC is the same as the pinout for the 74LS00 quad NAND IC. It is always a good idea to review the data sheet before using any logic chip.
Another consistency is in the pin numbering scheme. If you orient the chip so that the pins are bending away from you and the end that has a notch or a dot is pointing to the left, pin 1 is the one at the lower left of the package. The numbering then proceeds sequentially around the chip in a counterclockwise direction, such that the highest-numbered pin is at the upper left. Almost always, when you orient the chip this way, the writing on the top will be right-side-up (see Fig. 10.2).
10.1.3 Logic gates
There are six basic logic gates, as shown in Fig. 10.3. These gates are sufficient to implement all logic functions, although the more complex functions are also available as specialized chips – multiplexers, decoders, etc. (to be discussed later) – which can simplify design as well as reduce cost. Although Fig. 10.3 shows only two-input gates, versions also exist with three, four, or even eight inputs.
Note that NAND and NOR are opposites to AND and OR: NAND equals not AND while NOR equals not OR. Also note that the NAND is a negative-logic OR while the NOR is a negative-negative-logic AND. (This follows from DeMorgan’s theorem, about which more below.) The small circle shown at the outputs of the NAND and NOR is shorthand for an inverter – a NAND is equivalent to an AND followed by an inverter, and similarly for NOR.
AND OR
Fig. 10.3. Standard logic gates with truth tables.
After the inverter, the NAND is the simplest logic gate to construct from discrete components, and historically it was the most commonly used gate.
NAND is a ‘universal’ logic function, in that the other logic functions can all be created using NAND gates. For example, connecting together the two inputs of a NAND creates a one-input gate – an inverter. Thus, if the output of a NAND is connected to both inputs of a second NAND, the result is equivalent to an AND gate.
10.1.4 Summary of Boolean algebra
Logic operations are best described using Boolean algebra. While a detailed exposition of Boolean algebra is beyond the scope of this text, we give here a brief introduction and mention a few useful points. Consider two logical variables A and B, which can take on the values true and false. We can then denote logic operations as follows:
r the logical AND of A and B is denoted as A· B;
As in any algebra, the rules of Boolean algebra allow theorems to be derived starting from axioms. An alternative way to prove a theorem in
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Fig. 10.4. DeMorgan’s theorems expressed symbolically.
Boolean algebra is by ‘exhaustive demonstration’, i.e., to write down the truth table – for every possible input state, work out the value of the output and write it down.
Two relationships (known as DeMorgan’s theorems) are particularly useful:
A· B = A + B. (10.1)
and
A+ B = A · B (10.2)
These are illustrated schematically in terms of logic gates as well as with truth tables in Fig. 10.4.