Digital Trunk Interface

EXERCISE OBJECTIVE

When you have completed this exercise, you will be able to explain the role of the digital trunk interface in a central office. You will be familiar with the DS1 and E1 TDM formats that can be used in the Lab-Volt digital trunk. You will be able to describe the operation of the digital trunk interface used in Lab-Volt CO's using the simplified block diagram of this interface.

DISCUSSION

Role of the Digital Trunk Interface

As mentioned before in this unit, a digital trunk is a link between two switching offices of the PSTN that can carry many digitized voice signals at a same time and in both directions. This is achieved by multiplexing in time digitized voice signals according to one of the various TDM formats available in the older North American and European hierarchies of digital transmission systems (DS1 to DS4 and E1 to E5 digital signals) and the SONET/SDH hierarchy of digital transmission systems (STS-1 to STS-192 and STM-1 to STM-64 electrical signals).

The role of the digital trunk interface is to provide a link between the digital circuitry of the CO (call processor, signaling circuit, and switching circuit) and a digital trunk.

This is illustrated in Figure 1-4.

Figure 1-4. The digital trunk interface provides a link between the digital circuitry of the CO and a digital trunk.

In brief, the digital trunk interface receives many digitized voice signals (64-kb/s PCM signals) from the switching circuit and signaling data from the call processor (via the signaling circuit). It time multiplexes these signals and data, according to a certain TDM format (DS1, E4, STS-1, STM-1, etc), to form a serial digital signal that is transmitted via the digital trunk line. Conversely, the digital trunk interface receives a serial digital signal corresponding to a certain TDM format (DS1, E4, STS-1, STM-1, etc) from the digital trunk line. It extracts (demultiplexes) the various digitized voice signals (64-kb/s PCM signals) and the signaling data it contains, and sends these signals and data to the switching circuit and the call processor (via the signaling circuit) of the CO, respectively. Note that depending on the TDM format used, the transmission media can be pairs of copper wires (as shown in Figure 1-4), coaxial cables, or optical fibers.

TDM Formats Used in the Lab-Volt Digital Trunk

Two TDM formats are available for the digital trunk used to interconnect Lab-Volt CO's. When the digitized voice signals are multiplexed in time over 24 time slots in Lab-Volt CO's, the DS1 format from the North American hierarchy of digital transmission systems is used. When time-division multiplexing is made over 32 time slots in Lab-Volt CO's, the E1 format from the European hierarchy of digital transmission systems is used.

Figure 1-5 illustrates the DS1 TDM format. This format divides time into intervals of equal duration that are referred to as frames. The duration of each frame is 125 μs, which exactly corresponds to the reciprocal of the sampling frequency (8 kHz) used in CO's to digitize voice signals. Each frame is subdivided into 24 time intervals that

Digital Trunk Interface

24 EIGHT-BIT SERIAL PCM CODES

FRAMING BIT (F BIT)

FRAME = FRAMING BIT + 24 EIGHT-BIT

125 μs TIME SLOTS (193 BITS) F

SIGNAL MAGNITUDE

23 EIGHT-BIT SERIAL PCM CODES PLUS 1 EIGHT-BIT WORD OF SIGNALING DATA

(192 BITS)

beginning of each frame to convey framing information (the use of this bit is covered later in this discussion). The F bit and the digitized voice signals in the 24 time slots form a serial digital signal which consists of 193 bits that repeat every frame, thereby leading to a bit rate of 1.544 Mb/s.

Figure 1-5. DS1 time-division multiplexing (TDM ) format.

Note that one of the 24 time slots in each DS1 frame can be used to convey signaling data (instead of a digitized voice signal) related to the digitized voice signals transmitted. This is the case in the Lab-Volt digital trunk where time slot 24 conveys signaling data and the remaining 23 time slots can carry digitized voice signals. Digital signaling between CO's is covered extensively in the next unit of this manual.

Figure 1-6 illustrates the E1 TDM format. This format also divides time into frames having a duration of 125 μs. Each frame is divided into 32 time slots that are numbered 0 to 31. Each of time slots 1 to 15 and 17 to 31 can carry a digitized voice signal (8-bit PCM code), for a maximum of 30 digitized voice signals. Time slot 0 is used to convey framing information (the use of this information is covered later in this discussion). Time slot 16 is used to convey signaling data related to the digitized voice signals transmitted. The 32 time slots form a serial digital signal which consists of 256 bits (32 time slots x 8 bits) that repeat every frame, thereby leading to a bit rate of 2.048 Mb/s.

Digital Trunk Interface

DIGITIZED VOICE SIGNAL (8-BIT SERIAL PCM CODE)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

b2 b5 b6

b7 b4 b3 b1 b0

MSB LSB

SIGN BIT

15 TIME SLOTS CONTAINING 15 EIGHT-BIT SERIAL PCM CODES

TIME SLOT CONTAINING SIGNALING INFORMATION TIME SLOT CONTAINING

FRAMING INFORMATION

FRAME = 32 EIGHT-BIT TIME SLOTS (256 BITS) 125 μs

SIGNAL MAGNITUDE

Figure 1-6. E1 time-division multiplexing (TDM) format.

Simplified Block Diagram of the DIGITAL TRUNK INTERFACE

Figure 1-7 is a simplified block diagram of the DIGITAL TRUNK INTERFACE used in Lab-Volt CO's. This diagram is divided in two major sections that are referred to as the RECEIVER and the TRANSMITTER. The RECEIVER receives a serial digital signal in DS1 or E1 format from the digital trunk line, extracts (demultiplexes) the various digitized voice signals and the signaling data it contains, and sends these signals and data to the switching circuit and the call processor (via the signaling circuit) of the CO, respectively. Conversely, the TRANSMITTER receives many digitized voice signals from the switching circuit and signaling data from the call processor (via the signaling circuit), time multiplexes these signals and data to form a DS1 or E1 digital signal that is transmitted via the digital trunk line.

The remaining two subsections in this discussion describe the operation of the circuitry in the RECEIVER and TRANSMITTER of the DIGITAL TRUNK INTERFACE.

Digital Trunk Interface

Figure 1-7. Simplified block diagram of the DIGITAL TRUNK INTERFACE used in Lab-Volt CO's.

Operation of the RECEIVER

The RECEIVER consists of a DATA/CLOCK RECOVERY CIRCUIT, a LINE DECODER, a FRAMING CIRCUIT AND ALARM DETECTOR, and TIME SLOT INTERCHANGER 1. The operation of each of these circuits is explained in this subsection. The explanations sometimes refer to the simplified block diagram in Figure 1-7.

DATA/CLOCK RECOVERY CIRCUIT

The DATA/CLOCK RECOVERY CIRCUIT receives a serial digital signal from the digital trunk line. This signal usually exhibits some distortion caused by the transmission over the digital trunk line. The DATA/CLOCK RECOVERY CIRCUIT

Digital Trunk Interface

1 1 0 1 0 1 0 0 1

BINARY SEQUENCE

SERIAL DIGITAL SIGNAL RECEIVED

RECOVERED BIT CLOCK SIGNAL

SIGNAL SERIAL DIGITAL REGENERATED

recovers the bit clock from the received serial digital signal. The bit clock is a square-wave signal having a frequency that corresponds to the bit rate (1.544 or 2.048 Mb/s) of the received digital signal. The recovered bit clock is used to synchronize the operation of the FRAMING CIRCUIT AND ALARM DETECTOR and TIME SLOT INTERCHANGER 1 with the incoming serial digital signal.

The DATA/CLOCK RECOVERY CIRCUIT uses the recovered bit clock to regenerate a "clean" serial digital signal from the distorted signal received from the digital trunk line. The regenerated serial digital signal is sent to the LINE DECODER.

Figure 1-8 shows a slightly distorted serial digital signal received from a digital trunk line and the RECOVERED BIT CLOCK signal and regenerated serial digital signal at the outputs of the DATA/CLOCK RECOVERY CIRCUIT. Notice that the rising edges in the RECOVERED BIT CLOCK signal are aligned with the middle of the pulses in the distorted serial digital signal to make the regeneration of the serial digital signal easier.

Figure 1-8. Input and output signals of the DATA/CLOCK RECOVERY CIRCUIT.

Note that the DATA/CLOCK RECOVERY CIRCUIT detects whether or not a signal is received from the digital trunk line. When a serial digital signal of sufficient magnitude is received from the digital trunk, the signal at the loss-of-signal (LOS)

Digital Trunk Interface

1 0 0 0 0 0 0 0 0

BINARY SEQUENCE

AMI CODED DIGITAL SIGNAL

HDB3 CODED DIGITAL SIGNAL

1 1 (NRZ FORMAT)

B8ZS CODED DIGITAL SIGNAL

VIOLATION BIPOLAR

LINE DECODER

The serial digital signal received from the digital trunk line is coded to ensure a minimal amount of transitions in this signal, and thereby, facilitates clock recovery.

When the DS1 TDM format is used, a line code referred to as bipolar with eight-zero substitution (B8ZS) is applied to the serial digital signal. When the E1 TDM format is used, another line code called high-density bipolar of order 3 (HDB3) is applied to the serial digital signal. In brief, the B8ZS and HDB3 line codes are modified versions of another line code called alternate mark inversion (AMI). When the AMI line code is used, each binary zero is transmitted as no signal on the line and each binary one is transmitted as a rectangular pulse whose polarity alternates from one binary one to the next. When the B8ZS line code is used, the serial digital signal is still AMI coded but each sequence of 8 successive binary zeroes in the digital signal is replaced with a sequence of pulses containing two bipolar violations, that is, a sequence where the alternation in pulse polarity is not respected. Similarly, when the HDB3 line code is used, the serial digital signal is also AMI coded but each sequence of 4 successive binary zeroes is replaced with a sequence of pulses containing one bipolar violation. Figure 1-9 shows a sequence of binary ones and zeros in non-return-to-zero (NRZ) format and the digital signals that result from AMI, B8ZS, and HDB3 line coding. Notice that the return-to-zero (RZ) format is used in each coded digital signal, that is, the duration of each pulse representing a binary one is equal to one half the bit interval.

Figure 1-9. Serial digital signals coded using the AMI, B8ZS, and HDB3 line codes.

Digital Trunk Interface

0 1 1 0 0 0 1 0 1

BINARY

LINE DECODER INPUT SIGNAL

SEQUENCE 0

OUTPUT SIGNAL LINE DECODER

The LINE DECODER in the RECEIVER of the DIGITAL TRUNK INTERFACE receives the serial digital signal regenerated by the DATA/CLOCK RECOVERY CIRCUIT, and converts this signal to the NRZ format. The resulting serial digital signal (recovered data) is sent to the FRAMING CIRCUIT AND ALARM DETECTOR and TIME SLOT INTERCHANGER 1. Figure 1-10 is an example of signals at the input and output of the LINE DECODER.

Figure 1-10. Signals at the input and output of the LINE DECODER.

FRAMING CIRCUIT AND ALARM DETECTOR

The FRAMING CIRCUIT analyzes the framing information contained in the serial digital signal coming from the LINE DECODER (recovered data) to find the beginning of each frame. This process is referred to as frame alignment, that is, the RECEIVER aligns itself with the serial digital signal received. Frame alignment is absolutely essential to correctly recover the digitized voice signals and the signaling data contained in the various time slots of each frame. When the FRAMING CIRCUIT is able to achieve frame alignment, a rectangular pulse signal appears at its RECOVERED FRAME SYNC. output, each pulse in this signal being aligned with the first time slot of each frame as shown in Figure 1-11. Furthermore, the signal at its loss-of-frame-alignment (LFA) output is at logic level zero. Conversely, the signal at the LFA output goes to logic level 1 when frame alignment is lost.

Digital Trunk Interface

FRAME SYNC.

SIGNAL

FRAME INTERVAL (125 μs)

TIME SLOT INTERVALS

BEGINNING OF A FRAME

RECOVERED

CLOCK SIGNAL TIME-SLOT RECOVERED

SYNC. SIGNAL MULTIFRAME RECOVERED

Figure 1-11. Output signals of the FRAMING CIRCUIT.

The FRAMING CIRCUIT also produces a recovered time-slot clock (RECOVERED TS CLOCK) signal and a recovered multiframe synchronization (RECOVERED MF SYNC.) signal. The RECOVERED TS CLOCK signal is a square-wave signal aligned with the time slot intervals. The RECOVERED MF SYNC. signal consists of a rectangular pulse that occurs at the beginning of each multiframe, the duration of this pulse being equal to one frame (125 μs).

Note: Appendix C of this manual provides information related to the multiframe structures of the DS1 and E1 digital signals.

The ALARM DETECTOR analyzes the serial digital signal coming from the LINE DECODER (recovered data) to detect the presence of remote alarm signals. When an alarm signal is detected, either the AIS or RAI output of the ALARM DETECTOR goes to logic level 1. Alarms are discussed extensively in the next exercise of this unit.

TIME SLOT INTERCHANGER 1

TIME SLOT INTERCHANGER 1 (TSI 1) receives a serial digital signal in NRZ format (recovered data) from the LINE DECODER. It performs time slot interchange, that is, it transfers digitized voice signals contained in certain time slots of the RECOVERED DATA signal to other time slots in the serial digital signal at its output (line TX2 of the DIGITAL TRUNK INTERFACE). For example, a digitized voice signal received in time slot 4 of the RECOVERED DATA signal can be made available in time slot 1 of the serial digital signal on line TX2, as shown in

Digital Trunk Interface

Figure 1-12. The use of time slot interchange in the DIGITAL TRUNK INTERFACE allows a digitized voice signal to be received from the digital trunk in a certain time slot while being space-division switched in another time slot in the switching circuit (space-division switch) of the CO. This flexibility greatly reduces the chances of having an inter-exchange call blocked because no communication path can be established. Data coming from the call processor of the CO determines what time slot interchanges are to be performed by TSI 1.

Figure 1-12. TIME SLOT INTERCHANGER 1 (TSI 1) performs time slot interchange and extracts signaling data contained in the RECOVERED DATA signal.

TSI 1 also extracts the signaling data contained in either time slot 16 or 24 of the RECOVERED DATA signal. The extracted signaling data, available at the DORX output of TSI 1, is sent to the call processor of the CO (via the digital signaling processor in the signaling circuit of the CO) where it is analyzed.

Notice that two bit clock signals and two frame synchronization signals are provided to TSI 1 shown in Figure 1-12. The RECOVERED BIT CLOCK and RECOVERED FRAME SYNC. signals, which are synchronized with the RECOVERED DATA signal, are used to write the contents of the RECOVERED DATA signal into the memory of TSI 1. Conversely, the BIT CLOCK and FRAME SYNC. signals from the CO are used to read the contents of the memory in TSI 1.

Operation of the TRANSMITTER

The TRANSMITTER consists of TIME SLOT INTERCHANGER 2, a FRAMING AND SIGNALING CIRCUIT, and a LINE CODER. The operation of each of these circuits is explained in this subsection. The explanations sometimes refer to the simplified block diagram in Figure 1-7.

Digital Trunk Interface

TIME SLOT INTERCHANGER 2

TIME SLOT INTERCHANGER 2 (TSI 2) receives digitized voice signals from the switching circuit (space-division switch) of the CO via line RX2. These digitized voice signals are to be transmitted to another CO via the digital trunk. TSI 2 performs time slot interchange to place the digitized voice signals to be transmitted in the proper time slots of the serial digital signal sent to the remote CO via the digital trunk. For example, if a digitized voice signal is received in time slot 3 and is to be transmitted in time slot 5 on the digital trunk, TSI 2 makes the digitized voice signal received from line RX2 during time slot 3 available during time slot 5 of the serial digital signal at its output. Data coming from the call processor of the CO determines the time slot interchanges that must be carried out by TSI 2 for the digitized voice signals to be transmitted via the digital trunk during the proper time slots. The BIT CLOCK and FRAME SYNC. signals from the CO are used to to read the contents of the memory in TSI 2.

Notice that two bit clock signals and two frame synchronization signals are provided to TSI 2 shown in Figure 1-7. The BIT CLOCK and FRAME SYNC. signals from the CO are used to write the contents of the serial digital signal on line RX2 into the memory of TSI 2. Conversely, the TX BIT CLOCK and TX FRAME SYNC. signals, which are synchronized with the TDM format used in the digital trunk, are used to read the contents of the memory of TSI 2.

The serial digital signal at the output of TSI 2 is sent to the FRAMING AND SIGNALING CIRCUIT. Note that when a time slot is not used to carry a digitized voice signal, the output signal of TSI 2 is held at logic level one. This adds a sequence of binary ones in the serial digital signal to be transmitted, and thereby, increases the number of transitions in the coded signal transmitted via the digital trunk. This feature of TSI 2 and the use of B8ZS or HDB3 line coding ensure easy clock recovery in the receiver at the other end of the digital trunk.

FRAMING AND SIGNALING CIRCUIT

The FRAMING AND SIGNALING CIRCUIT (FSC) adds framing information and signaling data to the serial digital signal coming from TSI 2.

The framing information is generated locally by the FSC. When the DS1 TDM format is used, the FSC inserts the framing information in the F bit position of each frame (bit located just before time slot 1). When the E1 TDM format is used, the FSC inserts the framing information in time slot 0 of each frame.

The FSC receives signaling data from the call processor of the CO, via the digital signaling processor in the signaling circuit of the CO and the DOTX input of the DIGITAL TRUNK INTERFACE. The signaling data is information exchanged between two CO's that allows control of inter-exchange calls. When the DS1 TDM format is used, the FSC inserts the signaling data in time slot 24 of each frame, one octet at a time. When the E1 TDM format is used, the FSC inserts the signaling data in time slot 16 of each frame. Note that the FSC inserts binary ones in time slot 24 or 16 whenever there is no signaling data to be transmitted. This adds a sequence of binary ones in the serial digital signal to be transmitted, and thereby, increases the number of transitions in the coded signal transmitted via the digital

Digital Trunk Interface

trunk. This helps in ensuring easy clock recovery in the receiver at the other end of the digital trunk.

Note that the FSC requires the TX BIT CLOCK and TX FRAME SYNC. signals from the CO in order to be able to insert the framing information and the signaling data into the correct time intervals of each frame.

LINE CODER

The LINE CODER applies a line code to the serial digital signal coming from the FRAMING AND SIGNALING CIRCUIT, which is in NRZ format, before transmission via the digital trunk. When the DS1 TDM format is used, the LINE CODER applies the B8ZS line code to the serial digital signal. When the E1 TDM format is used, the LINE CODER applies the HDB3 line code to the serial digital signal. The use of

In document Analog Access to the Telephone Network (Page 105-133)