Digitization

Analog-to-Digital converter

There are several ADC architectures, which differ in quantization resolution, conversion speed, power consumption, area, and design complexity. For the digitization of SiPM charge informa- tion, an ADC with a resolution of 9 ∼ 12 bit and conversion speed of several mega-samples per second is required. Moreover, the power consumption and area should be as small as possible in the multi-channel ASIC design. The Wilkinson ADC, the successive-approximation register (SAR) ADC, and the two-steps ADC are among the most suitable candidates.

Figure 4.6(a) shows a block diagram of a Wilkinson ADC, consisting of a ramp generator, a comparator, an AND gate, and a counter generates the output digital code. The ramp signal vt with a pre-defined slope compares with the sampled input voltage vs. The length

of the comparator output pulse or the edges of the gated clock at the AND output will be recorded by the output counter, representing the amplitude of the sampled input signal. The Wilkinson ADC has been widely used in SiPM readout electronics, such as SPIROC [37] and PETIROC [80]. In SPIROC, the conversion speed of around 10 kHz is very low and the analog memory has to be adapted to temporarily store the analog signals. Moreover, the ramp signal suffers a lot from the non-linearity and is sensitive to PVT variations, causing many troubles for the system integration.

(a) (b)

(c)

Figure 4.6: Block diagram of the (a) Wilkinson, (b) SAR, and (c) Two-steps ADC.

Another popular structure is the SAR ADC, as shown in Figure 4.6(b). It consists of a comparator, DAC, and digital SAR logic as the controller. The full conversion is performed over multiple clock cycles with a comparison-and-decision operation in each cycle. Depending on the comparator output after each comparison, the SAR logic sets the DAC input bits to generate the appropriate voltage for the next comparison [82]. Using a successive approximation algorithm (e.g. binary search algorithm), N+1 clocks are required for an N-bit SAR ADC. The SAR ADC is superior to the Wilkinson ADC in many aspects such as better linearity and more power-efficiency because of the absence of the power-hungry amplifier. The speed can be much faster to reach 40 Ms/s at 10-bit resolution in the 0.13 µm CMOS technology [83,84], which is the common-used technology node in nuclear electronics.

However, the quantization resolution of the SAR ADC is limited to around 10-bit by the silicon area constraint in a multi-channel design. To achieve higher resolution in an area-efficient way, the two-steps ADC is a good option. As depicted in Figure 4.6(c), the high-resolution conversion is accomplished by two low-resolution ADCs that operate in two steps sequentially. In the first step, the coarse ADC resolves the MSBs from the sampled input voltage and a residual voltage is generated by subtracting the DAC output from the sampled input voltage. Second, the fine ADC quantizes the amplified residual voltage. The increase of the quantization resolution is achieved at the cost of power consumption and design complexity. Nevertheless, it is still affordable especially when the ADC works in an event-driven mode.

There are other common ADC topologies in the literature. The flash ADC, which performs (2N−1)-level quantization with an equal number of comparators, provides the fastest conversion but with low resolution (<6 bits) and high power consumption. The pipelined ADC exploits the concept of two-stage ADC with the pipeline technique whereby multiple conversions overlapped in execution at the same time. It provides fast conversion and high resolution at the cost of high calibration complexity and high power consumption from the residual amplifiers. The sigma- delta (Σ−∆) ADC provides high resolution at a reasonable power consumption by employing the oversampling and noise-shaping techniques. However, it is a non-Nyquist ADC and thus provides no sample-to-sample conversion, making it unsuitable for SiPM applications. Other hybrid architectures emerging in recent time, such as time-interleaved and noise-shaping SAR DAC, are also not perfectly suitable for SiPM applications.

Time-to-digital converter

Similar to the ADC that digitizes the voltage difference between two signals, the TDC is essentially an electronics which quantizes the time difference between two signals (usually termed as "start" and "stop") and provides digital representations of this time interval. It has been widely used in many applications in scientific research (experiments in high-energy physics and astronomy), industry (medical instrumentations and commercial electronics) and telecommunications (high-speed data transfer). A comprehensive review of the TDC structures and their working principles can be found in [85].

The counter-based TDC is one of the oldest and simplest schemes where the time difference is measured by the number of clock edges counted during the time interval. The practical limitation of the counter-based method is the low quantization resolution, which is reverse proportional to the clock frequency. However, a substantial advantage for this method is the long dynamic range (DR) achievable in fairly simple circuitry, which makes it popular in hybrid with other precise TDC structures.

Another early TDC approach converts the time interval into the voltage difference through a time-to-voltage converter (TVC) and subsequently digitizes this voltage by a classical ADC. The main disadvantages of this technique are the large nonlinearities induced by the switching activities of the TVC, a long conversion time from the ADC and relatively large static power consumption.

The need for fine time resolution in many applications has resulted in the development of TDC architectures based on the propagation latency of the delay cells. One of the generic structure is the time-coding delay line TDC built with a series of delay elements and latch components. The output of the delay element will be reset when the rising-edge of the start signal passes through it. The states of the delay elements are latched at the rising edge of the stop signal. The conversion result is determined by the states of the outputs of latches and represented in thermometer coding format. The bin-size of the TDC thus equals to the latency of the delay cell. The time resolution of this TDC can be further improved by the use of the Vernier principle [86]. The main disadvantage of the delay line TDC is that the bin-size is not well controlled and suffers from PVT variations.

In order to obtain a well-defined bin-size, a feedback loop is introduced in the delay line to refer the bin-size to the number of delay elements and the period of the reference clock, which is reliable regardless of the PVT variations. In the delay-lock loop (DLL)-based TDC approach, the feedback loop contains a voltage-controlled delay line (VCDL). In the ideal case, the delay time of each delay cell equals the period of the reference clock divided by the number of cells in the delay line. The rising edge of the reference clock usually serves as the start signal, while the stop indicates the arrival of the event. A DLL-based TDC usually provides superior jitter performance when a clean reference clock is available. To further improve the time resolution of this architecture, one can try to divide the delay of the delay cells by performing phase interpolation using an array of DLLs or RC interpolation techniques.

Recently, some innovations in circuit design have emerged to push the TDCs jitter perfor- mance down to sub-picosecond level. These examples are cyclic TDCs using pulse-shrinking delay lines, gated ring oscillator TDCs and pipelined TDCs based on time amplifier, etc [87]. However, those techniques, which frequently appear in the design of the all-digital phase-locked loop, are largely driven by the CMOS technology scaling and hence are not suitable for appli- cations where analog signal processing is inevitable.